OXCFU950_07 Datasheet, PDF (45/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
8.3 Reset Configuration
8.3.1 Host Reset
After a hardware reset or soft reset (bit 7 of COR register),
all writable registers are reset to 0x00, with the following
exceptions:
1. DLL—reset to 0x01.
2. CPR—reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 00000002
TFL[6:0]: 00000002
LSR[7:0]: 0x60 signifying that both the transmitter and the
transmitter FIFO are empty
MSR[3:0]: 00002
MSR[7:4]: Dependent on modem input lines DCD, RI, DSR
and CTS respectively
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx000002
RFC[7:0]: 000000002
GDS[7:0]: 000000012
DMS[7:0]: 000000102
8.4 Transmitter & Receiver FIFOs
The transmitter and receiver holding registers (FIFOs), are
referred to as THR and RHR respectively.
In normal operation, when the transmitter finishes
transmitting a byte it removes the next data from the top of
the THR and transmits it. If the THR is empty, it waits until
data is written into it. If THR is empty and the last character
transmission is complete (i.e. the transmitter shift register is
empty) the transmitter is said to be idle. Similarly, when the
receiver finishes receiving a byte, it transfers it to the
bottom of the RHR. If the RHR is full, an overrun condition
occurs (see section 8.5.3).
Data is written into the bottom of the THR queue and read
from the top of the RHR queue completely asynchronously
to the operation of the transmitter and receiver.
FIFO size depends on the setting of the FiCR register. In
byte mode, FIFOs only accept one byte at a time before
indicating that they are full; this is compatible with the
16C450. In a FIFO mode, the size of the FIFOs is either 16
(compatible with the 16C550) or 128.
OXCFU950 DATA SHEET
The reset state of output signals are tabulated below:
Signal
SOUT
RTS#
DTR#
Reset state
Inactive High
Inactive High
Inactive High
Table 19: Output Signal Reset State
8.3.2 Software Reset
An additional feature available in the 950 core is software
resetting of the serial channel. The software reset is
available using the CSR register. Software reset has the
same effect as a hardware reset. To reset the UART, write
0x00 to the CSR.
Data written to the THR when it is full is lost. Data read
from the RHR when it is empty is invalid. The empty or full
status of the FIFOs is indicated in LSR (see section 8.5.3).
Interrupts can be generated or DMA signals can be used to
transfer data to/from the FIFOs. The number of items in
each FIFO may also be read back from the transmitter
FIFO level (TFL) and receiver FIFO level (RFL) registers
(see section 8.11.2).
8.4.1 4-Byte Access to THR & RHR
As with the OX16C95x UARTs, the OXCFU950 THR and
RHR registers can be accessed via the standard 550
compatible register space. See Table 13.
In the OXCFU950, the THR and RHR registers can also be
accessed at four contiguous locations in the OXCFU950
specific register locations. See Table 16.
Note: the same RHR data is read irrespective of which of
the four byte locations are read. Similarly, writing to any of
the additional THR locations has the same effect as writing
to any other—all four locations provide duplicate addresses
to the same THR or RHR register.
DS-0023 February 2007
External—Free Release
Page 45 of 74