OXCFU950_07 Datasheet, PDF (48/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
8.5.3 Line Status Register—LSR
This register provides the status of data transfer to CPU.
LSR[0]: RHR data available
logic 0 ⇒ RHR is empty: no data available
logic 1 ⇒ RHR is not empty: data is available to be read.
LSR[1]: RHR overrun error
logic 0 ⇒ No overrun error.
logic 1 ⇒ Data was received when the RHR was full. An
overrun error has occurred. The error is
flagged when the data would normally have
been transferred to the RHR.
LSR[2]: Received data parity error
logic 0 ⇒ No parity error in normal mode or 9^th bit of
received data is 0 in 9-bit mode.
logic 1 ⇒ Data has been received that did not have
correct parity in normal mode or 9^th bit of
received data is ‘1’ in 9-bit mode.
The flag is set when the data item in error is at the top of
the RHR, and cleared following a read of the LSR. In 9-bit
mode, LSR[2] is no longer a flag and corresponds to the 9^th
bit of the received data in RHR.
LSR[3]: Received data framing error
logic 0 ⇒ No framing error.
logic 1 ⇒ Data was received with an invalid stop bit.
This status bit is set and cleared in the same manner as
LSR[2]. When a framing error occurs, the UART tries to re-
synchronize by assuming that the error was due to
sampling the start bit of the next data item.
LSR[4]: Received break error
logic 0 ⇒ No receiver break error.
logic 1 ⇒ The receiver received a break.
OXCFU950 DATA SHEET
A break condition occurs when the SIN line goes low
(normally signifying a start bit) and stays low throughout
the start, data, parity and first stop bit. (Note: the SIN line is
sampled at the bit rate). A zero character with associated
break flag set is transferred to the RHR, and the receiver
then waits until the SIN line returns high. The LSR[4] break
flag is set when this data item gets to the top of the RHR
and is cleared following a read of the LSR.
LSR[5]: THR empty
logic 0 ⇒ Transmitter FIFO (THR) is not empty.
logic 1 ⇒ Transmitter FIFO (THR) is empty.
LSR[6]: Transmitter and THR empty
logic 0 ⇒ The transmitter is not idle
logic 1 ⇒ THR is empty and the transmitter has
completed the character in shift register and is
in idle mode. (I.e. set whenever the transmitter
shift register and the THR are both empty.)
LSR[7]: Receiver data error
logic 0 ⇒ Either there are no receiver data errors in the
FIFO or it was cleared by an earlier read of
LSR.
logic 1 ⇒ At least one parity error, framing error or break
indication in the FIFO.
In 450 mode LSR[7] is permanently cleared, otherwise this
bit is set when an erroneous character is transferred from
the receiver to the RHR. It is cleared when the LSR is read.
Note that in 16C550 this bit is only cleared when all of
the erroneous data are removed from the FIFO. In 9-bit
data framing mode parity is permanently disabled, so this
bit is not affected by LSR[2].
DS-0023 February 2007
External—Free Release
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