OXCFU950_07 Datasheet, PDF (43/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
Register access notes:
Note 0: Offset from function base address in I/O space
Note 1: Requires LCR[7] = 0
Note 2: Requires ACR[7] = 0
Note 3: Requires that last value written to LCR was not 0xBF
Note 4: To read this register ACR[7] must be = 0
Note 5: To read this register ACR[6] must be = 0
Note 6: Requires ACR[7] = 1
Note 7: Only bits 0 and 1 of this register can be written
Note 8: To read this register ACR[6] must be = 1
Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set
Note 10: TFL, RFL and GDS are available at two locations, accessing via the OXCFU950 specific register location being the most simple
Note 11: The 32-bit FIFO Access registers can also be accessed at 0x00 through 0x03, when DBURST is set to 0x01. This is for systems
where the UART must be mapped to an 8-byte address space.
Register SPR R/W
Name Offset ¹²
Indexed Control Register Set
ACR
0x00
R/W
CPR
0x01
R/W
Bit 7
Additiona
l
Status
Enable
TCR
0x02
R/W
0x03
R/W
TTL
0x04
R/W Unused
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICR
950
DTR definition and AutoDSR Tx
Rx
Read Trigger
control
Flow Disable Disable
Enable Level
Control
Enable
Enable
5-bit integer part of
3-bit fractional part of
clock prescaler
clock prescaler
Unused
4 Bit N-times clock
selection bits [3:0]
Unused
Transmitter Interrupt Trigger Level (0-127)
RTL
0x05
R/W Unused
Receiver Interrupt Trigger Level (1-127)
FCL
0x06
R/W Unused
Automatic Flow Control Lower Trigger Level (0-127)
FCH
0x07
R/W Unused
ID1
0x08
R
ID2
0x09
R
ID3
0x0A
R
Automatic Flow Control Higher Trigger level (1-127)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0xC9)
Hardwired ID byte 1 (0x50)
REV
0x0B
R
Hardwired revision byte (0x0B)
CSR
NMR
MDM
RFC
GDS¹³
DMS
0x0C
0x0D
0x0E
0X0F
0X10
0x11
PIDX
0x12
0x13
DS-0023 February 2007
W
Writing 0x00 to this register will reset the UART
R/W
Unused
9^th Bit
9^th Bit
9^th Bit
9^th Bit 9^th-bit Int. 9 Bit
SChar 4 Schar 3 SChar 2 SChar 1
En.
Enable
R/W
Unused
Disable Δ DCD Trailing Δ DSR Δ CTS
wake-up Wakeup RI edge Wakeup Wakeup
sensitivity _disable disable _{disable disable}
R FiCR[7] FiCR[6] FiCR[5] FiCR[4] FiCR[3] FiCR[2] FiCR[1] FiCR[0]
R
Unused
Good
Data
Status
R/W Force
Force
internal internal
TxRdy RxRdy
inactive inactive
Unused
Internal
TxRdy
status
(R)
Internal
RxRdy
status
(R)
R
Hardwired Port Index ( 0x00 )
R/W
Unused
Table 17: Indexed Control Register Set
External—Free Release
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