OXCFU950_07 Datasheet, PDF (14/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
4.1.2 Internal Voltage Regulator Supply De-Coupling
Adequate output supply decoupling is mandatory to reduce ripple and avoid oscillations—use two capacitors in parallel on the
REG_1V8 pin:
• One external 470-pF (or 1-nF) NPO capacitor must be connected between REG_VDD1V8 (pin #27) & VSS as close to the
chip as possible
• One external 2.2-μF (or 3.3-μ F) X7R capacitor must be connected between REG_VDD1V8 (pin #27) & VSS as close to
the chip as possible
Note : Z5u and Y5V capacitors must be avoided—the poor high-frequency behavior of these dielectrics makes them unsuitable
for power supply decoupling.
Adequate input supply decoupling is mandatory to improve start-up stability and reduce source voltage drop_
• One external 100-pF NPO capacitor must be connected between REG_VDDV3V (pin #28) & VSS as close to the chip as
possible
• One external 4.7-μ F X7R capacitor must be connected between REG_VDD3V3 (pin #28) & VSS as close to the chip as
possible
4.2 Oscillator Specification
Code
Parameter
Condition
Min
Typ
Max
Unit
Ton
Startup Time
With crystal defined below
2
ms
Pon
Drive level
150
μW
ESR
Equivalent series resistance
80
Ohm
Cm
Motion capacitance
5
9
fF
Cshunt
Shunt capacitance
7
pF
Cload
Load Capacitance
Max external capacitors: 40 pF 15
20
pF
XTLI and XTLO shall not be used to drive other circuits.
The external capacitors on XTLI and XTLO must have the correct crystal load capacitance (max 40 pF). Additionally, a 500-KΩ
pull-down resistor is required on XTLI.
4.3 I/O Pins for EEPROM Direct Access Programming Mode
The OXCFU950 allows a direct access mode to the internal EEPROM, for programming the EEPROM without using the PC Card
Interface. This can be used by manufacturers to configure The EEPROM during board manufacture.
The following table shows the pins used for this EEPROM programming mode.
Pin Name
TEST
A6
A5
A4
A8
A9
READY
Z_IORD
A7
Z_WE
Z_IOWR
Direction
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Pin Usage Description
Test mode enable signal (Set to ‘logic 1’ – VDD3V3)
Static test signal (set to logic ‘1’ – VDD3V3)
Static test signal (set to‘logic ‘1’ – VDD3V3)
Static test signal (set to logic ‘0’ – VSS)
Serial data in (SDI)
Shift & load
Serial data out (SDO)
Test clock input
Write-enable signal to write in the memory (active-low)
Reset signal
EEPROM test-enable signal
Full details of the internal configuration of the EEPROM and details of programming utilities are available on request from Oxford
Semiconductor.
DS-0023 February 2007
External—Free Release
Page 14 of 74