OXCFU950_07 Datasheet, PDF (12/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
Pin Number
Pad Type^{Note 1}
Pin Name
57
I_C_33_5_N_ RI#
1
P_33
UART_VDD3V3
Crystal Oscillator / PLL pins^Note4
51
A_18
50
A_18
XTLO
XTLI
49
P_18
PLL_VSS1V8
48
P_18
PLL_VDD1V8
USB^{Note 5}
2
3
4
Multi-Purpose I/O^{Note 3}
64,63,62,61
A_33
A_33
P_33
B_T_33_5_N_1_
USB_DP
USB_DM
USB_VDD3V3
MIO[3:0]
Miscellaneous Pins/Pads^Note2
52
I_C_33_5_N_U
20
I_C_33_5_N_D
Additional Power and Ground
65 (Thermal bonding P_00
pad)
27
P_18
CIS_MODE
TEST
VSS
REG_VDD1V8
Table 1: Pin Descriptions
Note 1 : Pad syntax description
Pad type
Digital Input pad
Digital Output pad
Digital Tristate output pad
Digital Bidirectional pad
Analogue pad
Power Pad
Table 2: Pad Type Syntax
syntax
t_a_xy_h_i_p
t_a_xy_d
t_a_xy_d
t_a_xy_h_i_d_p
t_xy
t_xy
Description
is enabled, upon de-assertion of the DSR# pin, the transmitter completes
the current character & enters idle mode until the DSR# pin is
reasserted. Note: flow control characters are transmitted regardless of
the state of the DSR# pin.
Active-low modem ring-indicator input.
Power supply to UART and MIO I/O interfaces. Voltage on these pins
should be tied to 1.8 V to 3.3 V supply (depending on requirement).
Crystal oscillator output.
Crystal oscillator input. Frequency = 12 MHz.
Note : a pull-down resistor of 500 KΩ is required on this pin.
Ground (0 Volts) for PLL & oscillator cells. This pin should be tied to
ground.
Power supply for PLL & oscillator cells. This pin should be tied to 1.8
volts (i.e. tied to REG_VDD1V8 pin).
USB data plus.
USB data minus.
Power supply to USB I/O interface. This pin should be tied to 3.3 volts.
Multipurpose IO pins.
Note: if enabled, MIO[3:0] can be used as an interrupt inputs.
MIO[3:2] can be configured to act as the USB power management
control signals PORT_OVER_CURRENT & PORT_POWER
Test mode select pin/default CIS select. (See Section 5.1)
Test pin. This pin should be tied to VSS for normal operation.
Main digital ground pin. The VSS pin should be tied to ground. Note this
is the thermal bonding pin underneath the 64-pin QFN package
Output supply from internal voltage regulator at 1.8 V. Can be used as
power supply to PLL (i.e. pin #48).
DS-0023 February 2007
External—Free Release
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