AR0330 Datasheet, PDF (9/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

Figure 3:
Typical Configuration: Serial MIPI
Digital Digital
I/O Core
power¹ power¹
AR0330: 1/3-Inch CMOS Digital Image Sensor
Working Modes
PLL
Analog Analog
power^{1 power1 power1}
Master clock
(6–27 MHz)
From
controller
VDD_IO VDD
EXTCLK
OE_BAR
TRIGGER
SADDR
SCLK
SDATA
RESET_BAR
TEST
DGND
VAA VAA_PIX
DATA1_P
DATA1_N
DATA2_P
DATA2_N
DATA3_P
DATA3_N
DATA4_P
DATA4_N
CLK_P
CLK_N
SHUTTER
FLASH
AGND
To
controller
(MIPI - serial interface)
Digital
ground
Analog
ground
VDD_IO
VDD
VDD_PLL
VAA
VAA_PIX
1.0μF 0.1μF 1.0μF 0.1μF 1.0μF 0.1μF 1.0μF 0.1μF 1.0μF 0.1μF
Notes: 1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0F
and 0.1F decoupling capacitors for every power supply. If space is a concern, then priority must be
given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_MIPI, VDD_IO, and VDD. Actual values and
results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1F decoupling capacitor
inside the module as close to the pads as possible. In addition, place a 10F capacitor for each sup-
ply off-module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
4. The pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. TEST pin must be tied to DGND for the MIPI configuration.
7. ON Semiconductor recommends that GND_MIPI be tied to DGND.
8. VDD_MIPI is tied to VDD_PLL in both the CLCC and the CSP package. ON Semiconductor strongly rec-
ommends that VDD_MIPI must be connected to a VDD_PLL in a module design since VDD_PLL and
VDD_MIPI are tied together in the die.
9. The package pins or die pads used for the HiSPi data and clock as well as the parallel interface must
be left floating.
10. HiSPi Power Supplies (VDD_HiSPi and VDD_HiSPi_TX) can be tied to ground.
11. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
12. If the TRIGGER or OE_BAR pins or pads are not used, then they should be tied to DGND.
AR0330_DS Rev. U Pub. 4/15 EN
9
©Semiconductor Components Industries, LLC,2015.