AR0330 Datasheet, PDF (30/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
HiSPi Transmitter
Clock Signal
t_HCLK is defined as the high clock period, and t_LCLK is defined as the low clock period as
shown in Figure 15. The clock duty cycle D_CYC is defined as the percentage time the clock
is either high (t_HCLK) or low (t_LCLK) compared with the clock period T.
Figure 15: Clock Duty Cycle
Figure 16:
D_CYC1
=
t_{--H----C---L---K-}
T
D_CYC0
=
t_{--L---C---L---K--}
T
t_pw
=
T_--
2
(i.e, 1 UI)
(EQ 9)
(EQ 10)
(EQ 11)
Bitrate = ---1---
t_pw
(EQ 12)
Figure 16 shows the definition of clock jitter for both the period and the cycle-to-cycle
jitter.
Clock Jitter
AR0330_DS Rev. U Pub. 4/15 EN
Period Jitter (t_CKJIT) is defined as the deviation of the instantaneous clock t_PW from an
ideal 1UI. This should be measured for both the clock high period variation t_HCLK, and
the clock low period variation t_LCLK taking the RMS or 1-sigma standard deviation and
quoting the worse case jitter between t_HCLK and t_LCLK.
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