AR0330 Datasheet, PDF (73/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Revision History
Revision History
Rev. U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/13/15
• Updated “Ordering Information” on page 2
Rev. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/10/15
• Updated to ON Template and Legal Disclaimer
• Updated Table 5, Pin Descriptions and Table 6, “CSP (HiSPi/MIPI) Package Pinout,”
on page 13 names for consistency on page 13
• Added HiSPi voltage information to Figure 6: “Power Up,” on page 15
• Updated Table 9, “DC Electrical Definitions and Characteristics (MIPI Mode),” on
page 18
• Added Parallel output information and MIPI information to Table 11, “DC Electrical
Definitions and Characteristics (Parallel Mode),” on page 19
• Updated Table 12, “Standby Power,” on page 19
• Updated Two Wire Serial Interface description for consistency - no change to the part
specification on page 20
• Updated HiSPi power names for consistency on pages 24 and 25
• Added Table 12, “Standby Power,” on page 19
Rev. R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/25/13
• Updated Table 3, “Available Aspect Ratios in the AR0330 Sensor,” on page 7
• Updated Table 5, “Pin Descriptions,” on page 12
• Updated “Power-Up Sequence” on page 15
• Updated “Dual Readout Paths” on page 33
• Updated “Output Enable Control” on page 36
• Updated Figure 30: “Gain Stages in AR0330 Sensor,” on page 44
• Updated Table 32, “Recommended Sensor Analog Gain Tables,” on page 44
• Deleted Table 34, “Available Skip and Bin Modes in the AR0330 Sensor”
• Updated Equation 23 on page 52
• Updated Table 37, “Minimum Vertical Blanking Configuration,” on page 52
• Updated “Frame Readout” on page 56
Rev. Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/8/13
• Updated master clock range in:
– Figure 2: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on page 8
– Figure 3: “Typical Configuration: Serial MIPI,” on page 9
– Figure 4: “Typical Configuration: Parallel Pixel Data Interface,” on page 10
– Table 5, “Pin Descriptions,” on page 12
• Updated note for Table 6, “CSP (HiSPi/MIPI) Package Pinout,” on page 13
• Updated Table 9, “DC Electrical Definitions and Characteristics (MIPI Mode),” on
page 18
• Updated Table 10, “DC Electrical Definitions and Characteristics (HiSPi Mode),” on
page 18
• Updated Table 16, “I/O Timing,” on page 22
• Updated Figure 19: “PLL for the Parallel Interface,” on page 33
• Updated Figure 20: “PLL for the Serial Interface,” on page 34
• Updated “Slave Address/Data Direction Byte” on page 61
AR0330_DS Rev. U Pub. 4/15 EN
73
©Semiconductor Components Industries, LLC,2015.