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AR0330 Datasheet, PDF (24/77 Pages) ON Semiconductor – CMOS Digital Image Sensor
AR0330: 1/3-Inch CMOS Digital Image Sensor
HiSPi Transmitter
Table 20: SLVS Electrical Timing Specification
Parameter
Symbol
Min
Max
Unit
Notes
Data Rate
Bitrate Period
Max setup time from transmitter
Max hold time from transmitter
Eye Width
Data Total Jitter (pk-pk) @1e-9
Clock Period Jitter (RMS)
Clock Cycle-to-Cycle Jitter (RMS)
Rise time (20% - 80%)
Fall time (20% - 80%)
Clock duty cycle
Mean Clock to Data Skew
PHY-to-PHY Skew
Mean differential skew
1/UI
tPW
tPRE
tPOST
tEYE
tTOTALJIT
tCKJIT
tCYCJIT
tR
tF
DCYC
tCHSKEW
tPHYSKEW
tDIFFSKEW
280
1.43
0.3
0.3
150ps
150ps
45
-0.1
-100
700
3.57
0.6
0.2
50
100
0.25
0.25
55
0.1
2.1
100
Mbps
1
ns
1
UI
1, 2
UI
1, 2
UI
1, 2
UI
1, 2
ps
2
ps
2
UI
3
UI
3
%
2
UI
1, 4
UI
1, 5
ps
6
Notes:
1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from the 0V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any
edges.
5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any
edges.
Differential skew is defined as the skew between complementary outputs. It is measured as the abso-
lute time between the two complementary edges at mean VCM point. Note that differential skew also
is related to the VCM_AC spec which also must not be exceeded.
HiVCM Electrical Specifications
The HiSPi 2.0 specification also defines an alternative signaling level mode called
HiVCM. Both VOD and VCM are still scalable with VDD_HiSPi_TX, but with VDD_HiSPi_TX
nominal set to 1.8 V the common-mode is elevated to around 0.9 V.
Table 21: HiVCM Power Supply and Operating Temperatures
Parameter
Symbol
Min
Typ
Max
Unit
HiVCM Current Consumption
HiSPi PHY Current Consumption
Operating temperature
IDD_HiSPi_TX
IDD_HiSPi
TJ
-30
n*34
mA
n*45
mA
70
°C
Notes:
1. Where 'n' is the number of PHYs
2. Temperature of 25°C
3. Up to 700 Mbps
4. Specification values may be exceeded when outside this temperature range.
Notes
1, 2
1, 2, 3
4
AR0330_DS Rev. U Pub. 4/15 EN
24
©Semiconductor Components Industries, LLC,2015.