AR0330 Datasheet, PDF (21/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Electrical Characteristics
Figure 9:
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum ^tHD;DAT has only to be met if the device does not stretch the LOW period (^tLOW) of
the SCLK signal.
6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement
t_{SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch}
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line ^tr max + ^tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I²C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing Diagram (Parallel Mode)
tR
tF
90%
10%
tRP
tFP
90%
10%
tEXTCLK
EXTCLK
PIXCLK
tPD
Data[11:0]
FRAME_VALID/
LINE_VALID
*PLL disabled for ^tCP
Pxl _0
tPFH
tPLH
tPD
Pxl _1
FRAME_VALID leads LINE_VALID by 609 PIXCLKs.
tCP
Pxl _2
Pxl _n
tPFL
tPLL
FRAME_VALID trails
LINE_VALID by 16 PIXCLKs.
Table 15:
I/O Parameters
f_{EXTCLK = 24 MHz; VDD = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; Output load = 68.5pF; TJ = 60°C;}
CLK_OP = 98 MPixel/s
Symbol
VIH
Definition
Input HIGH voltage
VIL
Input LOW voltage
IIN
Input leakage current
VOH
Output HIGH voltage
VOL
Output LOW voltage
IOH
Output HIGH current
IOL
Output LOW current
IOZ
Tri-state output leakage current
Conditions
VDD_IO = 1.8V
VDD_IO = 2.8V
VDD_IO = 1.8V
VDD_IO = 2.8V
No pull-up resistor; VIN = VDD OR
DGND
At specified IOH
At specified IOL
At specified VOH
At specified VOL
Min
1.4
2.4
GND – 0.3
GND – 0.3
– 20
Max
VDD_IO + 0.3
0.4
0.8
20
VDD_IO - 0.4V
–
–
0.4
–
–12
–
9
–
10
Units
V
A
V
V
mA
mA
A
AR0330_DS Rev. U Pub. 4/15 EN
21
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