AR0330 Datasheet, PDF (37/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Pixel Output Interfaces
High Speed Serial Pixel Data Interface
The High Speed Serial Pixel (HiSPi) interface uses four data and one clock low voltage
differential signaling (LVDS) outputs.
• SLVSC_P
• SLVSC_N
• SLVS0_P
• SLVS0_N
• SLVS1_P
• SLVS1_N
• SLVS2_P
• SLVS2_N
• SLVS3_P
• SLVS3_N
The HiSPi interface supports three protocols, Streaming S, Streaming SP, and Packetized
SP. The streaming protocols conform to a standard video application where each line of
active or intra-frame blanking provided by the sensor is transmitted at the same length.
The Packetized SP protocol will transmit only the active data ignoring line-to-line and
frame-to-frame blanking data.
These protocols are further described in the High-Speed Serial Pixel (HiSPi™) Interface
Protocol Specification V1.00.00.
The HiSPi interface building block is a unidirectional differential serial interface with
four data and one double data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple lanes. Figure 21 shows the
configuration between the HiSPi transmitter and the receiver.
Figure 21: HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing
the HiSPi transmitter
Dp0
Dn0
Dp1
Dn1
Tx
Dp2
PHY0
Dn2
Dp3
Dn3
Cp0
Cn0
A host (DSP) containing
the HiSPi receiver
Dp0
Dn0
Dp1
Dn1
Dp2
Rx
Dn2 ^PHY0
Dp3
Dn3
Cp0
Cn0
AR0330_DS Rev. U Pub. 4/15 EN
37
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