AR0330 Datasheet, PDF (34/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Sensor PLL
Table 25: PLL Parameters for the Parallel Interface
Parameter
External Clock
VCO Clock
Readout Clock
Output Clock
Symbol
EXTCLK
F_VCO
CLK_PIX
CLK_OP
Min
Max
6
27
384
768
49
98
Unit
MHz
MHz
Mpixel/s
Mpixel/s
Table 26: Example PLL Configuration for the Parallel Interface
Parameter
F_VCO
vt_sys_clk_div
vt_pix_clk_div
CLK_PIX
CLK_OP
Output pixel rate
Value
1
6
Output
588 MHz (Max)
49 Mpixel/s (= 588 MHz / 12)
98 Mpixel/s (= 588 MHz / 6)
98 MPixel/s
Serial PLL Configuration
Figure 20: PLL for the Serial Interface
Fvco
EXTCLK
6-27 MHz
pre_pll_clk_div
2(1-64)
pll_multiplier
58(32-384)
vt_sys_clk_div
1(1, 2, 4, 6, 8,
10, 12, 14, 16)
vt_pix_clk_div
6(4-16)
CLK_PIX
op_sys_clk_div
op_pix_clk_div
Fvco
Constant - 1
12(8, 10, 12)
CLK_OP
FSERIAL
1/2
FSERIAL_CLK
The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per
lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4)
configured. To configure the sensor protocol and number of lanes, refer to “Serial
Configuration” on page 40.
AR0330_DS Rev. U Pub. 4/15 EN
34
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