AR0330 Datasheet, PDF (31/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
HiSPi Transmitter
Cycle-to-cycle jitter (t_CYCJIT) is defined as the difference in time between consecutive
clock high and clock low periods t_HCLK and t_LCLK, quoting the RMS value of the variation
(t_HCLK - t_LCLK).
If pk-pk jitter is also measured, this should be limited to ±3-sigma.
Table 24: HiVCM Electrical AC Specification
Notes:
Parameter
Data Rate
Bitrate Period
Max setup time from transmitter
Max hold time from transmitter
Eye Width
Data Total Jitter (pk-pk) @1e-9
Clock Period Jitter (RMS)
Clock Cycle-to-Cycle Jitter (RMS)
Rise time (20% - 80%)
Fall time (20% - 80%)
Clock duty cycle
Clock to Data Skew
PHY-to-PHY Skew
Mean differential skew
Symbol
1/UI
t_PW
t_PRE
t_POST
t_EYE
t_TOTALJIT
t_CKJIT
t_CYCJIT
t_R
t_F
D_CYC
t_CHSKEW
tP_HYSKEW
t_DIFFSKEW
Min
280
1.43
0.3
0.3
150ps
150ps
45
-0.1
-100
Max
700
3.57
0.6
0.2
50
100
0.3
0.3
55
0.1
2.1
100
Unit
Mbps
ns
UI
UI
UI
UI
ps
ps
UI
UI
%
UI
UI
ps
Notes
1
1
1, 2
1, 2
1, 2
1, 2
2
2
3
3
2
1, 4
1, 5
6
1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from the 0 V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3 UI.
4. The absolute mean skew between the clock lane and any data lane in the same PHY between any
edges.
5. The absolute mean skew between any clock in one PHY and any data lane in any other PHY
between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point. Note that differential
skew also is related to the VCM_AC spec which also must not be exceeded.
AR0330_DS Rev. U Pub. 4/15 EN
31
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