AR0330 Datasheet, PDF (32/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

Sequencer
AR0330: 1/3-Inch CMOS Digital Image Sensor
Sequencer
The sequencer digital block determines the order and timing of operations required to
sample pixel data from the array during each row period. It is controlled by an instruc-
tion set that is programmed into RAM from the sensor OTPM (One Time Programmable
Memory). The OTPM is configured during production.
The instruction set determines the length of the sequencer operation that determines
the “ADC Readout Limitation” (Equation 5) listed in the Sensor Frame-Rate section. The
instruction set can be shortened through register writes in order to achieve faster frame
rates. Instructions for shortening the sequencer can be found in the AR0330 Developer
Guide.
The sequencer digital block can be reprogrammed using the following instructions:
Program a new sequencer.
1. Place the sensor in standby.
2. Write 0x8000 to R0x3088 (“seq_ctrl_port”).
3. Write each instruction incrementally to R0x3086. Each write must be 16-bit consisting
of two bytes {Byte[N], Byte[N+1]}.
4. If the sequencer consists of an odd number of bytes, set the last byte to “0”.
Read the instructions stored in the sequencer.
1. Place the sensor in standby.
2. Write 0xC000 to R0x3088 (“seq_ctrl_port”).
3. Sequentially read one byte at a time from R0x3086 with 8-bit read command.
Sensor PLL
VCO
Figure 17: Relationship Between Readout Clock and Peak Pixel Rate
EXTCLK
pre_pll_clk_div
(6-27 MHz)
2 (1-64)
pll_multiplier
F_VCO
58 (32-384)
The sensor contains a phase-locked loop (PLL) that is used for timing generation and
control. The required VCO clock frequency is attained through the use of a pre-PLL clock
divider followed by a multiplier. The multiplier is followed by set of dividers used to
generate the output clocks required for the sensor array, the pixel analog and digital
readout paths, and the output parallel and serial interfaces.
AR0330_DS Rev. U Pub. 4/15 EN
32
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