AR0330 Datasheet, PDF (45/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

Data Pedestal
AR0330: 1/3-Inch CMOS Digital Image Sensor
Data Pedestal
Each digital gain can be configured from a gain of 0 to 15.875. The digital gain supports
128 gain steps per 6dB of gain. The format of each digital gain register is “xxxx.yyyyyyy”
where “xxxx” refers an integer gain of 1 to 15 and “yyyyyyy” is a fractional gain ranging
from 0/128 to 127/128.
The sensor includes a digital dithering feature to reduce quantization resulting from
using digital gain can be implemented by setting R0x30BA[5] to 1. The default value is 0.
Refer to “Real-Time Context Switching” on page 47 for the analog and digital gain regis-
ters in both context A and context B modes.
Refer to “Real-Time Context Switching” on page 57 for the analog and digital gain regis-
ters in both context A and context B modes.
The data pedestal is a constant offset that is added to pixel values at the end of datapath.
The default offset is 168 and is a 12-bit offset. This offset matches the maximum range
used by the corrections in the digital readout path.
The data pedestal value can be changed if the lock register bit (R0x301A[3]) is set to “0”.
This bit is set to “1” by default.
AR0330_DS Rev. U Pub. 4/15 EN
45
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