AR0330 Datasheet, PDF (35/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Sensor PLL
Table 27: PLL Parameters for the Serial Interface
Parameter
External Clock
VCO Clock
Readout Clock
Output Clock
Output Serial Data Rate Per Lane
Output Serial Clock Speed Per Lane
Symbol
EXTCLK
F_VCO
CLK_PIX
CLK_OP
F_SERIAL
F_{SERIAL_CLK}
Min
6
384
300 (HiSPi)
384 (MIPI)
150 (HiSPi)
192 (MIPI)
Max
27
768
98
98
700 (HiSPi)
768 (MIPI)
350(HiSPi)
384 (MIPI)
Unit
MHz
MHz
Mpixel/s
Mpixel/s
Mbps
MHz
The serial output should be configured so that it adheres to the following rules:
• The maximum data-rate per lane (F_SERIAL) is 768Mbps/lane (MIPI) and 700Mbps/
lane (HiSPi).
• The output pixel rate per lane (CLK_OP) should be configured so that the sensor
output pixel rate matches the peak pixel rate (2 x CLK_PIX).
– 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 196 Mpixel/s)
– 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 98 Mpixel/s)
– 1-lane: 1 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 76 Mpixel/s)
Table 28: Example PLL Configurations for the Serial Interface
Parameter
F_VCO
vt_sys_clk_div
vt_pix_clk_div
op_sys_clk_div
op_pix_clk_div
F_SERIAL
F_{SERIAL_CLK}
CLK_PIX
CLK_OP
Pixel Rate
4-lane
12-bit
10-bit
588
490
1
1
6
5
1
1
12
10
588
490
294
245
98
98
49
49
196
196
2-lane
12-bit
10-bit
588
490
2
2
6
5
1
1
12
10
588
490
294
245
49
49
49
49
98
98
12-bit
768
4
6
1
12
768
384
32
64
64
1-lane
10-bit
768
4
5
1
10
768
384
38.4
76.8
76.8
8-bit
768
4
4
1
8
768
384
48
96
96
Notes
MHz
MHz
MHz
Mpixel/s
Mpixel/s
Mpixel/s
AR0330_DS Rev. U Pub. 4/15 EN
35
©Semiconductor Components Industries, LLC,2015.