AR0330 Datasheet, PDF (55/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Slave Mode
Figure 38:
Slave Mode Example Where the Integration Period is Half of the Frame Readout Period
The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration
caused by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of
16.6ms while the integration time is configured to 8.33ms.
Frame
Valid
VD Signal
Rising
Edge
Rising
Edge
Rising
Edge
Slave Mode
Trigger
Row 0
Inactive
8.33 ms 8.33 ms
Active
Inactive
Active
Row reset and read
operations begin after
the rising edge of the
Vd signal.
Row Reset
(start of integration)
Row Readout
Programmed Integration
Integration due to
Slave Mode Delay
Row N
Reset operation is
held during slave
mode “Active” state.
When the slave mode becomes active, the sensor will pause both row read and row reset
operations.
Note: The row integration period is defined as the period from row reset to row read.
When the AR0330 is working in slave mode, the external trigger signal VD must have
accurately controlled timing to avoid uneven exposure in the output image. The VD
timing control should make the slave mode “wait period” less than 32 pixel clocks.
To avoid uneven exposure, programmed integration time cannot be larger than VD
period. To increase integration time more than current VD period, the AR0330 must be
configured to work at a lower frame rate and read out image with new VD to match the
new timing.
The period between slave mode pulses must also be greater than the frame period. If the
rising edge of the VD pulse arrives while the slave mode is inactive, the VD pulse will be
ignored and will wait until the next VD pulse has arrived.
AR0330_DS Rev. U Pub. 4/15 EN
55
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