AR0330 Datasheet, PDF (12/77 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0330: 1/3-Inch CMOS Digital Image Sensor
Pin Descriptions
Pin Descriptions
Table 5:
Pin Descriptions
Name
RESET_BAR
EXTCLK
OE_BAR
TRIGGER
SADDR
SCLK
SDATA
PIXCLK
DOUT[11:0]
FLASH
FRAME_VALID
LINE_VALID
VDD
VDD_IO
VDD_PLL
DGND
VAA
VAA_PIX
AGND
TEST
SHUTTER
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
DATA1_P
DATA1_N
DATA2_P
DATA2_N
DATA3_P
DATA3_N
DATA4_P
DATA4_N
CLK_P
CLK_N
Type
Input
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
Power
Power
Power
Power
Power
Power
Power
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Asynchronous reset (active LOW). All settings are restored to factory default.
Master input clock, range 6 -27 MHz
Output enable (active LOW). Only available on bare die version.
Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame.
Two-wire serial address select.
Two-wire serial clock input.
Two-wire serial data I/O.
Pixel clock out. DOUT is valid on rising edge of this clock.
Parallel pixel data output.
Flash output. Synchronization pulse for external light source. Can be left floating if not used.
Asserted when DOUT data is valid.
Asserted when DOUT data is valid.
Digital power.
IO supply power.
PLL power supply. The MIPI power supply (VDD_MIPI) is tied to VDD_PLL in both packages.
Digital GND.
Analog power.
Pixel power.
Analog GND.
Enable manufacturing test modes. Tie to DGND for normal sensor operation.
Control for external mechanical shutter. Can be left floating if not used.
HiSPi serial data, lane 0, differential P.
HiSPi serial data, lane 0, differential N.
HiSPi serial data, lane 1, differential P.
HiSPi serial data, lane 1, differential N.
HiSPi serial data, lane 2, differential P.
HiSPi serial data, lane 2, differential N.
HiSPi serial data, lane 3, differential P.
HiSPi serial data, lane 3, differential N.
HiSPi serial DDR clock differential P.
HiSPi serial DDR clock differential N.
MIPI serial data, lane 1, differential P
MIPI serial data, lane 1, differential N
MIPI serial data, lane 2, differential P
MIPI serial data, lane 2, differential N
MIPI serial data, lane 3, differential P
MIPI serial data, lane 3, differential N
MIPI serial data, lane 4, differential P
MIPI serial data, lane 4, differential N
Output MIPI serial clock, differential P
Output MIPI serial clock, differential N
AR0330_DS Rev. U Pub. 4/15 EN
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