NP8P128A13BSM60E Datasheet, PDF (7/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
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Product Overview
The Numonyx® Omneo™ P8P PCM provides the convenience and ease of NOR flash
emulation while providing a set of Super Set features that exploit the inherent
capabilities of the PCM technology. The device emulates most of the features of the
Numonyx™ Axcel™ Embedded Memory (P33). This is intended to ease the evaluation
and design of Numonyx® Omneo™ P8P PCM into existing hardware and software
development platforms. This basic features set is supplemented by the Super Set
Features. The Super Set Features are intended to allow the designer to exploit the
inherent capabilities of the phase change memory technology, and to enable the
eventual simplification of hardware and software in the design. This section describes
an overview of the features and capabilities of Numonyx® Omneo™ P8P PCM.
• Density: Numonyx® Omneo™ P8P PCM product family begins with a 128-Mbit
density.
• Packages: Numonyx® Omneo™ P8P PCM devices are available in 64 Ball Easy
BGA and 56 Lead TSOP packages. These are the same pinouts and packages as the
existing P33 NOR flash devices.
• Low Power: Designed for low voltage systems, Numonyx® Omneo™ P8P PCM
supports read, write and erase operations at a core supply of 2.7V V_CC. P8P offers
additional power savings through standby mode. Standby mode is initiated when
the system deselects the device by driving CE inactive, which significantly reduces
power consumption.
• NOR-Compatible Program and Emulated Erase Operation: Numonyx®
Omneo™ P8P PCM provides a complete set of commands that are compatible with
industry-standard command sequences used by NOR-type flash. An internal Write
State Machine (WSM) automatically executes the algorithms and timings necessary
for block erase and write. Each emulated block erase operation results in the
contents of the addressed block being written to all “1s” (ones). Data can be
programmed in word or buffer increments. Erase-suspend allows system software
to pause an erase command so it can read or program data in another block.
Program suspend allows system software to pause programming so it can read
from other locations within the device. The Status Register indicates when the
WSM’s block erase, or program operation is finished.
• Write Buffer: A 64 byte/32 word Write Buffer is also included to allow optimum
write performance. By using the write buffer, data is overwritten or programmed in
buffer increments. This feature improves system program performance more than
20 times over independent byte writes.
• Command User Interface: As with floating gate flash, a Command User Interface
(CUI) serves as the interface between the system processor and internal operation
of the device. A valid command sequence written to the CUI initiates device
automation.
• Data Protection: Numonyx® Omneo™ P8P PCM block locking enables zero-
latency block locking/unlocking and permanent locking. Permanent block locking
provides enhanced security for boot code. The combination of these two locking
features provides complete locking solution for code and data.
• CFI Compliant: A flash-compatible Common Flash Interface (CFI) permits
software algorithms to be used for entire families of devices. This allows device-
independent, JEDEC ID-independent, and forward- and backward-compatible
software support for the specified flash device families.
July 2010
316144-07
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