NP8P128A13BSM60E Datasheet, PDF (37/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
11.1.1
11.2
11.2.1
11.2.2
11.2.3
Note:
Clear Status Register Command
The Clear Status Register command clears the Status Register. The command functions
independently of the applied V_PP voltage. The WSM can set (1) Status Register bits
SR[7:0] and clear (0) bits 2, 6, and 7. Because bits 1, 3, 4 and 5 indicate various error
conditions, they can only be cleared by the Clear Status Register command. By allowing
system software to reset these bits, several operations (such as cumulatively
programming several addresses or erasing multiple blocks in sequence) may be
performed before reading the Status Register to determine error occurrence. The
Status Register should be cleared before beginning another command or sequence.
Device reset (RST# = V_IL) also clears the Status Register.
System Protection Registers
The device contains two 64-bit, and sixteen 128-bit individually lockable protection
registers that can increase system security or hinder device substitution by containing
values that mate the PCM component to the system’s CPU or ASIC.
One 64-bit protection register is programmed at the Numonyx factory with an non-
changeable unique 64-bit number. The other 64-bit and sixteen 128-bit protection
registers are blank so customers can program them as desired. Once programmed,
each customer segment can be locked to prevent further reprogramming.
Read Protection Register
The Read Identifier command allows Protection register data to be read 16 bits at a
time from addresses shown in Table 9, “Read Identifier Table” on page 22. To read the
Protection Register, first issue the Read Device Identifier command at Device Base
Address to place the device in the Read Device Identifier mode. Next, perform a read
operation at the device’s base address plus the address offset corresponding to the
register to be read. Table 9, “Read Identifier Table” on page 22 shows the address
offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a
time. Refer Appendix , “Protection Register Addressing” on page 39.
Program Protection Register
The Protection Program command should be issued followed by the data to be
programed at the specified location. It programs the 64 user protection register 16 bits
at a time. Table 9, “Read Identifier Table” on page 22 and in Table 18 on page 39 show
allowable addresses. See also Figure 36, “Protection Register Programming Flowchart”
on page 79. Addresses A[MAX:11] are ignored when programming the OTP, and OTP
program will succeed if A[10:1] are within the prescribed protection addressing range;
otherwise an error is indicated by SR4 = 1.
Lock Protection Register
Each of the protection registers are lockable by programming their respective lock bits
in the PR-LOCK0 or PR-LOCK1 registers. Bit 0 of the Lock-Register -0 is programmed by
Numonyx to lock-in the unique device number. The physical address of the PR-LOCK0
register is 80h as seen in Figure 8, “Protection Register Memory Map” on page 38. Bit 1
of the Lock-Register -0 can be programmed by the user to lock the upper 64-bit
portion. (Refer Table 18, “Protection Register Addressing” on page 39.). The bits in
both PR-LOCK registers are made of “PCM cells” that may only be programmed to ‘0’
and may not be altered.
Bit0 of the Lock-Register, PR-LOCK0, is a don’t care, so users must mask out this bit
when reading PR-LOCK0 register. This number is guaranteed to persist through board
attach.
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