NP8P128A13BSM60E Datasheet, PDF (51/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
12.4.6 Read data bytes (READ)
The device is first selected by driving Chip Select (S#) Low. The instruction code for the
read data bytes (READ) instruction is followed by a 3-byte address A[23:0], each bit
being latched-in during the rising edge of Serial Clock (C). Then the memory contents,
at that address, is shifted out on serial data output (Q), each bit being shifted out, at a
maximum frequency f_R, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single read data bytes (READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S#) High.
Chip Select (S#) can be driven High at any time during data output. Any read data
bytes (READ) instruction, while an erase, program, write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 14: Read data bytes (READ) instruction sequence and data-out sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address (1)
DQ0
DQ1
High Impedance
23 22 21
MSB
3210
Data out 1
Data out 2
76543 2107
MSB
AI13736b
July 2010
316144-07
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