NP8P128A13BSM60E Datasheet, PDF (52/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
12.4.7 Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S#) Low. The instruction code for the
read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte
address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of
Serial Clock (C). Then the memory contents, at that address, are shifted out on serial
data output (Q) at a maximum frequency f_C, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single read data bytes at higher speed
(FAST_READ) instruction. When the highest address is reached, the address counter
rolls over to 000000h, allowing the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving
Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data
output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase,
program, write, or cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 15: Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-bit address (1)
DQ0
DQ1
High Impedance
23 22 21 3 2 1 0
S
C
DQ0
DQ1
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy byte
76543210
DATA OUT 1
DATA OUT 2
76543210765432107
MSB
MSB
MSB
AI13737b
Datasheet
52
July 2010
316144-07