NP8P128A13BSM60E Datasheet, PDF (33/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
Figure 6: Block Locking State Diagram
Power-Up/Reset
Locked
[x01 ]
Locked -
Down ^{4, 5}
[ 011]
Hardware
Locked ⁵
[011 ]
WP# Hardware Control
Unlocked
[x00 ]
Software
Locked
[ 111]
Unlocked
[ 110]
Notes:
S oftw are B loc k Loc k (0x 60/ 0x 01) or S oftw are B loc k Unloc k (0x60/ 0x D0)
S oftw are B loc k Loc k -D ow n (0x 60/0x 2F)
WP # hardware c ontrol
1. [a,b,c] represents[WP#, DQ1, DQ0]. X = Don’t Care
2. DQ1 indicates Block Lock -Down status. DQ1 = ‘0’, Lock-Down has not bee issued to this block.
DQ1 = ’1', Lock-Down has been issued to this block.
3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked . DQ0 = ‘1’, block is locked .
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked system software to determine difference between Hardware
Locked and Locked-Down states.
10.2
Permanent One Time Programmable (OTP) Block Locking
The parameter blocks and first 3 main blocks for a bottom parameter device (or if
device configured as a top parameter device this would be the last 3 main blocks and
the parameter blocks) can be made OTP, so further write and erase operations to these
blocks are disallowed, effectively permanently programming the blocks. This is
achieved by programming bits 2, 3, 4, and 5 in the PR-LOCK0 register at offset 0x80 in
ID Space. The OTP locking bit mapping may be seen in Table 15, “Selectable OTP Block
Locking Feature” on page 34 below.
Bit 6 in the PR-LOCK0 register at offset 0x80 in ID space is defined as the Configuration
Lock bit. When bit 6 is cleared (at zero), the device shall disable further programming
of the OTP Lock bits, thereby effectively “freezing” their state. Putting bit 6 at zero shall
not affect the ability to write any other bits in the non OTP regions or in the System
Protection Registers. Reference Table 16, “Selectable OTP Block Locking Programming
of PR-LOCK0” on page 34 for Configuration Lock bit (Bit 6 in PR-LOCK0) control of
allowed states when other bits of the register are programmed.
The read operations of these permanently locked blocks are always supported
regardless of the state of their corresponding Permanent Lock bits. Zero Latency Block
Locking must be used until the block is permanently locked with the OTP Block Locking.
Program and erase operations for these blocks remain fully supported until that block’s
Permanent Lock bit is cleared.
Program or erase operations to a permanently locked block returns a Status Register
bit SR.1 error.
Programming of the Permanent OTP Block Locking bits is not allowed during Erase
Suspend of a Permanent Lockable Block.
July 2010
316144-07
33