NP8P128A13BSM60E Datasheet, PDF (48/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
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Table 7. Protected area sizes
Status register contents
Memory content
TB BP BP BP BP
bit bit 3 bit 2 bit 1 bit 0
Protected area
Unprotected area
00
0
0
0 none
All sectors¹ (Sectors 0 to 127)
00
0
0
1 Upper 128th (Sector 127)
Sectors 0 to 126
00
0
1
0 Upper 64th (Sectors 126 to 127)
Sectors 0 to 125
00
0
1
1 Upper 32nd (Sectors 124 to 127)
Sectors 0 to 123
00
1
0
0 Upper 16th (Sectors 120 to 127)
Sectors 0 to 119
00
1
0
1 Upper 8th (Sectors 112 to 127)
Sectors 0 to 111
00
1
1
0 Upper quarter (Sectors 96 to 127)
Sectors 0 to 95
00
1
1
1 Upper half (Sectors 64 to 127)
0
1 X⁽²⁾ X⁽²⁾ X⁽²⁾ All sectors (Sectors 0 to 127)
10
0
0
0 none
Sectors 0 to 63
None
All sectors⁽¹⁾ (Sectors 0 to 127)
10
0
0
1 Lower 128th (Sector 0)
Sectors 1 to 127
10
0
1
0 Lower 64th (Sectors 0 to 1)
Sectors 2 to 127
10
0
1
1 Lower 32nd (Sectors 0 to 3)
Sectors 4 to 127
10
1
0
0 Lower 16th (Sectors 0 to 7)
Sectors 8 to 127
10
1
0
1 Lower 8th (Sectors 0 to15)
Sectors 16 to 127
10
1
1
0 Lower 4th (Sectors 0 to 31)
Sectors 32 to 127
10
1
1
1 Lower half (Sectors 0 to 63)
1
1 X⁽²⁾ X⁽²⁾ X⁽²⁾ All sectors (Sectors 0 to 127)
Sectors 64 to 127
None
1. The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP3, BP2, BP1, BP0) are 0
2. X can be 0 or 1
1.
12.4.4.4
12.4.4.5
Top/bottom bit
Reads as 0
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the write
protect (W) signal. The status register write disable (SRWD) bit and the write protect
(W) signal allow the device to be put in the hardware protected mode (when the status
register write disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In
this mode, the non-volatile bits of the status register (SRWD, TB, BP3, BP2, BP1, BP0)
become read-only bits and the write status register (WRSR) instruction is no longer
accepted for execution.
Datasheet
48
July 2010
316144-07