NP8P128A13BSM60E Datasheet, PDF (44/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
Table 20: Instruction set
Instruction
Description
WREN
WRDI
RDID
RDSR
WRSR
READ
FAST_READ
PP
SE
Write enable
Write disable
Read identification
Read status register
Write status register
Read data bytes
Read data bytes at higher speed
Page program (Legacy Program)
Page program (Bit-alterable write)
Page program (On all 1’s)
Sector erase
One-byte instruction code
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
0010 0010
1101 0001
1101 1000
06h
04h
9Fh
05h
01h
03h
0Bh
02h
22h
D1h
D8h
Address Dummy
bytes
bytes
0
0
0
0
0
0
0
0
0
0
3
0
3
1
3
0
3
0
3
0
3
0
Data
bytes
0
0
1 to 3
1 to ∞
1
1 to ∞
1 to ∞
1 to 64
1 to 64
1 to 64
0
12.4.1 Write enable (WREN)
The write enable (WREN) instruction sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every page program (PP), sector
erase (SE), or write status register (WRSR) instruction.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending
the instruction code, and then driving Chip Select (S) High.
Figure 9: Write enable (WREN) instruction sequence
S
C
DQ0
DQ1
01234567
Instruction
High Impedance
AI13731
Datasheet
44
July 2010
316144-07