NP8P128A13BSM60E Datasheet, PDF (16/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
4.0
Signals
Table 5: Ball/Pin Descriptions
Symbol
A[MAX:1]
DQ[15:0]
CE# or S#
OE# or
HOLD#
RST#
WE#
WP#
C
D
Q
SERIAL
V_PP
V_CC
V_CCQ
V_SS
V_SSQ
NC
DU
RFU
Type
Name and Function
Input
ADDRESS INPUTS: Device address inputs. 128-Mbit: A[23:1]
Note: that the address bus for TSOP and Easy BGA starts at A1. Numonyx® Omneo™ P8P PCM uses x16
addressing. The package is x8 addressing to be compatible with J3 or P30 products.
Input/
Output
Input
DATA INPUT/OUTPUTS: Inputs data and commands during writes (internally latched). Outputs data
during read operations. Data signals float when CE# or OE# are V_IH. or RST# is V_IL.
CHIP ENABLE: CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. CE#-
high deselects the device, places it in standby state, and places data outputs at high-Z.
SPI
SPI Select: S# low activates command writes to the SPI interface. Rising S# to VIH completes (or
terminates) the SPI command cycle; it also sets Q to high-Z.
Input
SPI
OUTPUT ENABLE: Active low OE# enables the device’s output data buffers during a read cycle. With
OE# at V_IH, device data outputs are placed in high-Z state.
SPI HOLD#: When asserted, suspends the current cycle and sets Q to high-Z until de-asserted.
Input
RESET CHIP: When low, RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. The device is in 8-Word
page mode array read after reset exits.
Input
WRITE ENABLE: controls Command User Interface (CUI) and array writes. Its rising edge latches
addresses and data.
Input
WRITE PROTECT: Disables/enables the lock-down function.
When WP# is V_IL, the lock-down mechanism is enabled and software cannot unlock blocks marked
lock-down.
When WP# is V_IH, the lock-down mechanism is disabled and blocks previously locked-down are
now locked; software can unlock and lock them. After WP# goes low, blocks previously marked lock-
down revert to that state.
SPI SPI Clock: Synchronization clock for input and output data
SPI
SPI Data Input: Serial data input for Op Codes, address and program data bytes. Input data is clocked
in on the rising edge of C, starting with the MSB.
SPI
SPI Data Output: Serial data output for read data. Output data is clocked out, triggered by the falling
edge of C, starting with the MSB.
SPI Enable: SERIAL is a port select switching between the normal parallel or serial interface. When Vss,
the normal (non-SPI) Numonyx® Omneo™ P8P PCM interface is enabled; all other SPI inputs are Don't
Care, and Q is at High-Z. When Vcc, SPI mode is enabled, all non-SPI inputs are Don't Care, and all
SPI _{outputs are at High-Z.}
This pin has an internal weak pull down resistor to select the normal parallel interface when users leave
the pin floating. A CAM can be used to permanently disable this feature.
ERASE AND WRITE POWER: A valid V_PP voltage allows erase or programming. Memory contents can’t
be altered when V_PP ≤ V_PPLK.
Pwr Set V_PP = V_CC for in-system program and erase operations. To accommodate resistor or diode drops from
the system supply, V_PP’s V_IH level can be as low as V_PPLMIN.
Program/erase voltage is normally 1.7 V–3.6 V.
Pwr
DEVICE POWER SUPPLY: Writes are inhibited at V_CC ≤ V_LKO. Device operations at invalid V_CC voltages
should not be attempted.
Pwr
OUTPUT POWER SUPPLY: Enables all outputs to be driven at V_CCQ. This input may be tied directly to
V_CC if V_CCQ is to function within the V_CC range.
Pwr GROUND: connects device circuitry to system ground.
Pwr I/O GROUND: Tie to GND
NO CONNECT: No internal connection; can be driven or floated.
DON’T USE: Don’t connect to power supply or other signals.
RESERVED FOR FUTURE USE: Don’t connect to other signals.
Datasheet
16
July 2010
316144-07