NP8P128A13BSM60E Datasheet, PDF (17/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
5.0
Bus Operations
CE# at V_IL and RST# at V_IH enables device read operations. Addresses are always
assumed to be valid. OE#-low activates the outputs and gates selected data onto the I/
O bus. WE#-low enables device write operations. When the VPP voltage ≤ VPPLK
(lockout voltage), only read operations are enabled.
Table 6: Bus Operations
State
RST#
CE#
OE#
WE#
DQ[15:0]
Note
Read (Main Array)
Read (Status, Query, Identifier)
Output Disable
Standby
Reset
Write
V_IH
V_IL
V_IL
V_IH
D_OUT
V_IH
V_IL
V_IL
V_IH
D_OUT
V_IH
V_IL
V_IH
V_IH
High-Z
V_IH
V_IH
X
X
High-Z
2
V_IL
X
X
X
High-Z
2
V_IH
V_IL
V_IH
V_IL
D_IN
1
Notes:
1.
See Table 8, “Command Sequences in x16 Bus Mode” on page 20 for valid D_IN during a write operation.
2.
X = Don’t care (L or H)
3.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
5.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
5.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7, “Command Codes and Descriptions” on
page 19 shows the bus cycle sequence for each of the supported device commands,
while Table 8, “Command Sequences in x16 Bus Mode” on page 20 describes each
command. See Section 16.0, “AC Characteristics” on page 62 for signal-timing details.
Note: Write operations with invalid V_CC and/or V_PP voltages can produce spurious results and should
not be attempted.
5.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
5.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, I_CCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
July 2010
316144-07
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