NP8P128A13BSM60E Datasheet, PDF (50/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
12.4.5 Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the
status register. Before it can be accepted, a write enable (WREN) instruction must
previously have been executed. After the write enable (WREN) instruction has been
decoded and executed, the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S#)
Low, followed by the instruction code and the data byte on serial data input (DQ0).
The write status register (WRSR) instruction has no effect on b1 and b0 of the status
register.
Chip Select (S#) must be driven High after the eighth bit of the data byte has been
latched in. If not, the write status register (WRSR) instruction is not executed. As soon
as Chip Select (S#) is driven High, the self-timed write status register cycle (whose
duration is t_W) is initiated. While the write status register cycle is in progress, the
status register may still be read to check the value of the write in progress (WIP) bit.
The write in progress (WIP) bit is 1 during the self-timed write status register cycle,
and is 0 when it is completed. When the cycle is completed, the write enable latch
(WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be
treated as read-only. The write status register (WRSR) instruction also allows the user
to set and reset the status register write disable (SRWD) bit in accordance with the
Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the hardware protected mode (HPM). The write
status register (WRSR) instruction is not executed once the hardware protected mode
(HPM) is entered.
Read Status Register (RDSR) is the only instruction accepted while WRSR operation is
in progress; all other instructions are ignored.
Figure 13: Write status register (WRSR) instruction sequence
S
C
DQ0
DQ1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
Status
register in
76543210
MSB
AI13735
Datasheet
50
July 2010
316144-07