NP8P128A13BSM60E Datasheet, PDF (21/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
Table 8: Command Sequences in x16 Bus Mode
Mode
Command
Bus
Cycles
First Bus Cycle
Oper Addr⁽¹⁾
Data⁽²⁾
Second Bus Cycle
Oper Addr⁽¹⁾ Data⁽²⁾
Block
Lock
Lock Block
Unlock Block
Lock-down Block
2
Write
BA
2
Write
BA
2
Write
BA
60h
Write
BA
60h
Write
BA
60h
Write
BA
01h
D0h
2Fh
Protection
Protection Program
Lock Protection Program
2
Write
PA
2
Write
LPA
C0h
C0h
Write
PA
Write
LPA
PD
FFFDh
Notes:
1.
First command cycle address should be the same as the operation’s target address.
X = Any valid address within the device.
IA = Identification code address.
BA = Address within the block.
LPA = Lock Protection Address (from the CFI). P8P LPA is at 0080h.
PA = 4-word protection address in the user programmable area of device identification plane.
DnA = Address within the device.
DBA = Device Base Address. (A[MAX:1]=0h)
PRA = Program Region
QA = Query code address.
WA = Word address of memory location to be written.
2.
SRD = Data read from the status register.
WD = Data to be written at location WA.
ID = Identifier code data.
PD =User programmable protection data.
QD = Query code data on DQ[7:0].
N = Data count to be loaded into the device to indicate how many words would be written into the buffer. Because the
internal registers count from 0, the user writes N-1 to load N words.
3.
The second cycle of the Buffered Program command, which is the count being loaded into the buffer is followed by data
streaming up to 32 words and then a confirm command is issued which triggers the programming operation. Refer to
the Appendix B, “Buffered Program Flowchart”.
July 2010
316144-07
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