NP8P128A13BSM60E Datasheet, PDF (45/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
12.4.2 Write disable (WRDI)
The write disable (WRDI) instruction resets the write enable latch (WEL) bit.
The write disable (WRDI) instruction is entered by driving Chip Select (S#) Low,
sending the instruction code, and then driving Chip Select (S#) High.
The write enable latch (WEL) bit is reset under the following conditions:
• Power-up
• Write disable (WRDI) instruction completion
• Write status register (WRSR) instruction completion
• Page program (PP) instruction completion
• Sector erase (SE) instruction completion
Figure 10: Write disable (WRDI) instruction sequence
S
C
DQ0
DQ1
01234567
Instruction
High Impedance
AI13732
July 2010
316144-07
45