NP8P128A13BSM60E Datasheet, PDF (34/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
Note:
The Selectable Block Locking will not be indicated in the Zero Latency Block Lock
Status. See Section 10.1.6, “Block Lock Status” on page 31 for more information. Read
PR-LOCK0 register to determine Block Lock Status for these blocks.
Table 15: Selectable OTP Block Locking Feature
Bit Number @ Offset
0x80 in CFI Space
Function When Set (‘1b)
2
Blocks not permanently locked
3
Block not permanently locked
4
Block not permanently locked
5
Block not permanently locked
6
Able to change PR-LOCK0[5:2] Bits
Function When Cleared (‘0b)
Write/erase disabled for all parameter blocks
Bottom Boot - Blocks 0-3
Top Boot 128M - Blocks 127-130
Write/erase disabled for first Main Block
Bottom Boot - Block 4
Top Boot 128M - Block 126
Write/erase disabled for second Main Block
Bottom Boot - Block 5
Top Boot 128M - Block 125
Write/erase disabled for third Main Block
Bottom Boot - Block 6
Top Boot 128M - Block 124
Program disabled for PR-LOCK0[5:2]
Table 16: Selectable OTP Block Locking Programming of PR-LOCK0
Bit 6
unlocked
locked
locked
locked
Program to
[5:2]
don’t care
YES
YES
NO
Program to
[1:0]
Status Register
don’t care
YES
NO
YES
no fail bits set
program fail/ lock fail
program fail/ lock fail
no fail bits set
Abort
Program
NO
YES
YES
NO
Status of Data in 80H OTP
Space
Changed
No Change
No Change
Changed
Figure 7: Selectable OTP Locking Illustration (Bottom Parameter Device Example)
Main Array Block 6
0x030000 (Main Array)
0x020000 (Main Array)
Main Array Block 5
Main Array Block 4
0x010000 (Main Array)
0x000000 (Parameter Array)
Parameter Blocks - Block 0-3
0x80 (OTP Array)
PR-LOCK0
65432
BOOT_ROM.WMF
Datasheet
34
July 2010
316144-07