NP8P128A13BSM60E Datasheet, PDF (43/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
Table 6.
Memory organization (Continued)
Sector
Address range
43
560000
57FFFF
7
0E0000
0FFFFF
6
0C0000
0DFFFF
5
0A0000
0BFFFF
4
080000
09FFFF
Sector
8
3
2
1
0
Address range
100000
060000
040000
020000
000000
11FFFF
07FFFF
05FFFF
03FFFF
01FFFF
12.4
Note:
SPI Instruction
Serial data input D is sampled on the first rising edge of Serial Clock (C) after Chip
Select (S#) is driven Low. Then, the one-byte instruction code must be shifted in to the
device, most significant bit first, on serial data input DQ0, each bit being latched on the
rising edges of Serial Clock (C).
The instruction set is listed in Table 20 on page 44.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or
none.
In the case of a read data bytes (READ), read data bytes at higher speed
(FAST_READ), read status register (RDSR) or read identification (RDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S#)
can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a page program (PP), sector erase (SE), write status register (WRSR),
write enable (WREN), or write disable (WRDI), Chip Select (S#) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.
That is, Chip Select (S#) must driven High when the number of clock pulses after Chip
Select (S#) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a write status register cycle, program
cycle erase cycle are ignored, and the internal write status register cycle, program
cycle, erase cycle continues unaffected.
Output Hi-Z is defined as the point where data out is no longer driven
July 2010
316144-07
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