NP8P128A13BSM60E Datasheet, PDF (68/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

16.5
SPI AC Specifications
Numonyx® Omneo™ P8P Datasheet
Sym
Parameter
F_C
F_C
F_R
T_CH
T_CL
T_CLCH
T_CHCL
T_SLCH
T_CHSL
T_DVCH
T_CHDX
T_CHSH
T_SHCH
T_SHSL
T_SHQZ
T_CLQV
T_CLQX
T_HLCH
T_CHHH
T_HHCH
T_CHHL
T_HHQX
T_HLQZ
T_WHSL
T_SHWL
Clock Frequency for all instructions except READ (0 to +70)
Clock Frequency for all instructions except READ (-30 to +85)
Clock Frequency for READ
Clock High Time
Clock Low Time
Clock Rise Time (peak to peak)
Clock Fall Time (peak to peak)
S# Active Setup Time (relative to C)
S# Active Hold Time (relative to C)
Data Input Setup Time
Data Input Hold Time
S# Active Hold Time (relative to C)
S# Inactive Hold Time (relative to C)
S# Deselect Time
Output Disable Time
Clock Low to Output Valid
Output Hold Time
HOLD# Assertion Setup Time (relative to C)
HOLD# Assertion Hold Time (relative to C)
HOLD# De-assertion Setup Time (relative to C)
HOLD# De-assertion Hold Time (relative to C)
HOLD# De-assertion to Output Low-Z
HOLD# De-assertion to Output High-Z
W# Setup Time
W# Hold Time
Notes:
1.
T_CH + T_CL must be greater than or equal to 1/F_C(max).
2.
Sampled, not 100% tested.
3.
Expressed as a slew-rate
4.
Only applicable as a constraint for a WRSR instruction when SRWD is set to 1.
Speed
Note
1
1
2, 3
2, 3
2
2
2
4
4
-All Speeds
Min
D.C.
D.C.
D.C.
9
9
0.1
0.1
5
5
2
5
5
5
100
0
5
5
5
5
20
100
Max
50
33
25
8
9
10
10
Units
MHz
MHz
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Datasheet
68
July 2010
316144-07