NP8P128A13BSM60E Datasheet, PDF (56/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
13.0 Power and Reset Specification
13.1
Power-Up and Power-Down
Upon power-up the flash memory interface is defined by the SERIAL pin being at Vss
(parallel) or Vcc (serial).
• During power-up if the SERIAL pin is at Vss the flash memory will be a x16 parallel
interface.
• During power-up if the SERIAL pin is at Vcc the flash memory will be a SPI
interface.
After the interface is defined it can not be changed until a full power-down is completed
and a power-up sequence is reinitiated.
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V_CC and V_CCQ should attain their minimum operating voltage before applying V_PP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
13.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 22: Power and Reset
Num Symbol
Parameter⁽¹⁾
Min
Max
Unit
P1 t_PLPH
P2 t_PLRH
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
100
-
ns
-
40
-
40
us
P3 t_VCCPH
V_CC Power valid to RST# de-assertion (high)
100
-
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if t_PLPH is < t_{PLPH MIN}, but this is not guaranteed.
3.
Not applicable if RST# is tied to Vcc.
4.
Sampled, but not 100% tested.
5.
When RST# is tied to the V_CC supply, device will not be ready until t_VCCPH after V_CC ≥ V_CCMIN.
6.
When RST# is tied to the V_CCQ supply, device will not be ready until t_VCCPH after V_CC ≥ V_CCMIN.
7.
Reset completes within t_PLPH if RST# is asserted while no erase or program operation is executing.
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
Datasheet
56
July 2010
316144-07