NP8P128A13BSM60E Datasheet, PDF (40/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory

Numonyx® Omneo™ P8P Datasheet
12.0
12.1
Note:
12.2
Serial Peripheral Interface (SPI)
SPI Overview
A Serial Peripheral Interface has been added as a secondary interface on Numonyx®
Omneo™ P8P PCM to enable low cost, low pin count on-board programming. This
interface gives access to the P8P memory by using only seven signals, instead of a
conventional parallel interface that may take 45 signals or more. The seven signals
consist of six SPI-only signals plus one signal that is shared with the conventional
interface.
When the SPI mode is enabled, all non-SPI P8P output signals are tri-stated, and all
non-SPI P8P inputs signals are ignored (made “don't care”). When the conventional
interface is enabled, the SPI-only output is tri-stated, and the SPI-only inputs are
ignored (made “don't care”).
The SPI interface can only be enable upon power-up, and to enable this interface the
SERIAL pin must be tied to Vcc for the interface to be factional. Once the SPI interface
is enable it is the only interface that can be accessed until the part is powered down.
The SPI mode may be disabled. Please contact Numonyx for more information.
SPI Signal Names
For P8P, the six additional SPI-only signals are implemented in addition to the power
pins. V_CC, V_CCQ, and V_PP are valid power pins during Serial mode and must be
connected during SPI mode operation. Four of the six additional SPI signals do not
share functions with the regular interface. For pin and signal descriptions of all P8P pins
see Table 5, “Ball/Pin Descriptions” on page 16. Two pins are shared between the
interface modes: S# is the same pin as CE#, and HOLD# is the same pin as OE#. The
signals that are unique to the SPI mode and require a separate connection are C, D, Q,
and SERIAL.
Datasheet
40
July 2010
316144-07