English
Language : 

NP8P128A13BSM60E Datasheet, PDF (65/92 Pages) Numonyx B.V – 128-Mbit Parallel Phase Change Memory
Numonyx® Omneo™ P8P Datasheet
16.4
AC Write Specifications
Table 31: AC Write Characteristics
Num
Sym
Parameter (1, 2)
Speed
Note
All Speeds
Min
Max
Units
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W16
tPHWL
tELWL
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
tQVBL
tBHWH
tWHGL
tWHQV
RST# high recovery to WE# low
CE# setup to WE# low
WE# write pulse width low
Data setup to WE# high
Address valid setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
VPP setup to WE# high
VPP hold from valid Status read
WP# hold from valid Status read
WP# setup to WE# high
WE# high to OE# low
WE# high to read valid
Write to Asynchronous Read Specifications
3
150
ns
10
0
ns
4
50
ns
50
ns
50
ns
10
0
ns
0
ns
0
ns
20
ns
3,6
200
ns
3,6
0
ns
3,6
0
ns
3,6
200
ns
8
0
ns
3, 5, 9
tAVQV+35
ns
W18
tWHAV
WE# high to Address valid
3, 5, 7
0
ns
Notes:
1.
Write timing characteristics during erase suspend are the same as write-only operations.
2.
CE#- or WE#-high terminates a write operation.
3.
Sampled, not 100% tested.
4.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
6.
VPP and WP# should be at a valid level without changing state until erase or program success is determined.
7.
This spec is only applicable when transitioning from a write cycle to an asynchronous read.
8.
When doing a read status operation following any command that alters the Status Register contents, W14 is 20ns.
9.
Add 10ns if the write operation results in a block lock status change, for subsequent read operations to reflect this change.
10.
Guaranteed by design.
July 2010
316144-07
65