GXM Datasheet, PDF (95/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Integrated Functions (Continued)
4.1.4 L1 Cache Controller
The GXm processor contains an on-board 16 KB unified
data/instruction L1 cache. It operates in write-back mode.
Since the memory controller is also on-board, the L1
cache requires no external logic to maintain coherency. All
DMA cycles automatically snoop the L1 cache. For
improved graphics performance, part of the L1 cache
operates as a scratchpad RAM to be used by the graphics
pipeline as a BLT Buffer.
The CD bit (Cache Disable, bit 30) in CR0 globally con-
trols the operating mode of the L1 cache. LCD and LWT,
Local Cache Disable and Local Write-through bits in the
Translation Lookaside Buffer, control the mode on a page-
by-page basis. Additionally, memory configuration control
can specify certain memory regions as non-cacheable.
If the cache is disabled, no further cache line fills occur.
However, data already present in the cache continues to
be used. For the cache to be completely disabled, the
cache must be invalidated with a WBINVD instruction
after the cache has been disabled.
Write-back caching improves performance by relieving
congestion on slower external buses. With four dirty bits,
the cache marks dirty locations on a double-word basis.
This further reduces the number of double-word bus write
operations needed during a replacement or flush opera-
tion.
The GXm processor will cache SMM regions. This speeds
up system management overhead to allow for hardware
emulation such as VGA.
The cache of the GXm processor provides the ability to
redefine 2 KB, 3 KB, or 4 KB of the L1 cache to be
scratchpad memory. The scratchpad area is memory
mapped to the upper memory region defined by the GCR
register (Index B8h). The valid bits for the scratchpad
RAM will always be true and the scratchpad RAM loca-
tions will never be flushed to memory. The scratchpad
RAM serves as a general purpose high speed RAM and
as a BLT buffer for the graphics pipeline. Incrementing
BLT buffer address registers have been added to enable
the graphics pipeline to access this memory as a BLT
buffer. A 16-byte line buffer dedicated to the graphics
pipeline accesses has been added to minimize graphics
interference with normal CPU operation.
Table 4-3 summarizes the registers contained in the L1
cache. These registers do not have default values and
must be initialized before use. Table 4-4 on page 96 gives
the register/bit formats.
Table 4-3. L1 Cache BitBLT Register Summary
Mnemonic Name
Function
L1_BB0_BASE
L1 Cache BitBLT 0 Base Address
Contains the address offset to the first byte of BLT Buffer 0 in the scratch-
pad memory.
L1_BB0_POINTER
L1 Cache BitBLT 0 Pointer
Contains the address offset to the current line of BLT Buffer 0 in the
scratchpad memory.
L1_BB1_BASE
L1 Cache BitBLT 1 Base Address
Contains the offset to the first byte of BLT Buffer 1 in the scratchpad mem-
ory.
L1_BB1_POINTER
L1 Cache BitBLT 1 Pointer
Contains the address offset to the current line of BLT Buffer 1 in the
scratchpad memory.
Note: For information on accessing these registers, refer to Section 4.1.6 “CPU_READ/CPU_WRITE Instructions”
on page 99.
Revision 3.1
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