GXM Datasheet, PDF (237/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Index
A
Absolute Maximum Ratings
183
AC Characteristics
186
Accessing
157
Address Spaces
60
Directory Table Entry (DTE)
73
DTE Cache
73
I/O Address Space
60
Memory Address Space
60
Memory Addressing Modes
61
Offset Mechanism
61
Page Frame Offset (PFO)
73
Page Table Entry (PTE)
73
Paging Mechanism
72
Translation Look-Aside Buffer
74
Address Translation
108
Application Register Set
40
B
BGA Ball Assignments by Ball Number
15
BGA Ball Assignments by Pin Name
17
BGA Ball Assignments Diagram
14
C
Cache
BB0_BASE
95
BB0_POINTER
95
BB1_BASE
95
BB1_POINTER
95
GCR register (Index B8h)
95
L1 cache
95
scratchpad memory
95
Write-back caching
95
Cache Controller
95
Cache Disable, bit 30
95
Cache Test Operations
58
call gate
69
Current Privilege Level
69
Descriptor Privilege Level
69
Descriptor Privilege Level in Destination
69
Descriptors Bit Definitions
69
Segment Selector Field
69
CCR1
System Management Memory Access
49
CCR1 Configuration Control Register 1 Index C1h
49
CCR2
Enable Suspend Pins
49
Lock NW Bit
49
Suspend on HALT
49
Write-Through Region 1
49
CCR2 Configuration Control Register 2 Index C2h
49
CCR3
Load/Store Serialize 1 GByte to 2 GBytes
49
Load/Store Serialize 2 GBytes to 3 GBytes
49
Load/Store Serialize 3 GBytes to 4 GBytes
49
Map Enable
49
NMI Enable
49
SMM Register Lock
49
CCR3 Configuration Control Register 3 Index C3h
49
CCR4
Directory Table Entry Cache
50
Enable CPUID Instruction
50
I/O Recovery Time
50
Memory Read Bypassing
50
SMI Nest
50
CCR4 Configuration Control Register 4 Index E8h
50
CCR7
Cyrix Extended MMX Instructions Enable
50
NMI Enabl
50
CCR7 Configuration Control Register 7 Index EBh
50
Clock Mode
24
Configuration Register Map
48
Control Registers
48
Device ID Registers
48
Graphics/VGA Related Registers
48
SMM Base Header Address Registers
48
Configuration Register Summary
47
Conforming Code Segments
69
Control Transfer
87
CPU_READ
99
CPU_READ/WRITE
EAX instructions
99
EBX instructions
99
CPU_WRITE
99
CPUID Instruction
208
EAX = 0000 0000h
208
EAX = 0000 0001h
208
EAX = 0000 0002h
209
EAX = 8000 0000h
210
EAX = 8000 0001h
210
EAX = 8000 0002h
211
EAX = 8000 0003h
211
EAX = 8000 0004h
211
EAX = 8000 0005h
211
CPUID Levels
208
CPUID Levels, Extended
210
CR0 Register
45
Alignment Check Mask
46
Cache Disable
46
Emulate Processor Extension
46
Monitor Processor Extension
46
Not Write-Through
46
Numerics Exception
46
Paging Enable Bit
45
Protected Mode Enable
46
Task Switched
46
Write Protect
46
CR2 Register
45
Page Fault Linear Address
45
CR3 Register
45
Page Directory Base Register
45
CR4 Register
45
Time Stamp Counter Instruction
45
D
DC Characteristics
185
Descriptor Bit Structure
67
Descriptor Types
87
Descriptors
Gate
67
gate
69
Interrupt
67
Task
67
Device Select
28
DEVSEL
28
DIMM
112
DIR0
Device ID
51
DIR0 Device Identification Register 0 Index FEh
51
DIR1
Device Identification Revision
51
DIR1 Device Identification Register 1 Index FFh
51
Revision 3.1
237
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