GXM Datasheet, PDF (115/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Integrated Functions (Continued)
4.3.6 Memory Cycles
Figures 4-5 through Figure 4-8 on page 117 illustrate vari-
ous memory cycles that the memory controller supports.
The following subsections describe some of the sup-
ported cycles.
SDRAM Read Cycle
Figure 4-5 shows a SDRAM read cycle. The figure
assumes that a previous ACT command has presented
the row address for the read operation. Note that the burst
length for the READ command is always two.
SDCLK
CS#
RAS#
CAS#
WE#
MA
DQM
MD
COL n
n
n+1
Figure 4-5. Basic Read Cycle with a CAS Latency of Two
Revision 3.1
115
www.national.com