GXM Datasheet, PDF (168/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Virtual Subsystem Architecture (Continued)
5.2.2 Video Refresh
VGA refresh is controlled by two units: the CRT controller
(CRTC) and the attribute controller (ATTR). The CRTC
provides refresh addresses and video control; the ATTR
provides the refresh datapath, including pixel formatting
and internal palette lookup.
The VGA back end contains two basic clocks: the dot
clock (or pixel clock) and the character clock. The Clock-
Select field of the Miscellaneous Output register selects a
“master clock” of either 25 MHz or 28 MHz. This master
clock, optionally divided by two, drives the dot clock. The
character clock is simply the dot clock divided by eight or
nine.
The VGA supports four basic pixel formats. Using text for-
mat, the VGA interprets frame buffer values as ASCII
characters, foreground/background attributes, and font
data. The other three formats are all “graphics modes”,
known as APA (All Points Addressable) modes. These for-
mats could be called CGA-compatible (odd/even four
bits/pixel), EGA-compatible (4-plane four bits/pixel), and
VGA-compatible (pixel-per-byte eight bits/pixel). The for-
mat is chosen by the ShiftRegister field of the Graphics
Controller Mode register.
The refresh address pipe is an integral part of the CRTC,
and has many configuration options. Refresh can begin at
any frame buffer address. The display width and the frame
buffer pitch (scan-line delta) are set separately. Multiple
scan lines can be refreshed from the same frame buffer
addresses. The LineCompare register causes the refresh
address to be reset to zero at a particular scan line, pro-
viding support for vertical split-screen.
Within the context of a single scan line, the refresh
address increments by one on every character clock.
Before being presented to the frame buffer, refresh
addresses can be shifted by 0, 1, or 2 bits to the left.
These options are often mis-named Byte, Word, and Dou-
bleword modes. Using this shifter, the refresh unit can be
programmed to skip one out of two or three out of four
DWORDs of refresh data. As an example of the utility of
this function, consider Chain 4 mode, described earlier.
Pixels written in Chain 4 mode occupy one out of every
four DWORDs in the frame buffer. If the refresh path is put
into “Doubleword” mode, the refresh will come only from
those DWORDs writable in Chain 4. This is how VGA
mode 13h works.
In text mode, the ATTR has a lot of work to do. At each
character clock, it pulls a DWORD of data out of the frame
buffer. In that DWORD, plane 0 contains the ASCII char-
acter code, and plane 1 contains an attribute byte. The
ATTR uses plane 0 to generate a font lookup address and
read another DWORD. In plane 2, this DWORD contains a
bit-per-pixel representation of one scan line in the appro-
priate character glyph. The ATTR transforms these bits
into eight pixels, obtaining foreground and background
colors from the attribute byte. The CRTC must refresh
from the same memory addresses for all scan lines that
make up a character row; within that row, the ATTR must
fetch successive scan lines from the glyph table so as to
draw proper characters. Graphics modes are somewhat
simpler. In CGA-compatible mode, a DWORD provides
eight pixels. The first four pixels come from planes 0 and
2; each 4-bit pixel gets bits [3:2] from plane 2, and bits
[1:0] from plane 0. The remaining four pixels come from
planes 1 and 3. The EGA-compatible mode also gets
eight pixels from a DWORD, but each pixel gets one bit
from each plane, with plane 3 providing bit 3. Finally,
VGA-compatible mode gets four pixels from each
DWORD; plane 0 provides the first pixel, plane 1 the next,
and so on. The 8 BPP mode uses an option to provide
every pixel for two dot clocks, thus allowing the refresh
pipe to keep up (it only increments on character clocks)
and meaning that the 320-pixel-wide mode 13h really has
640 visible pixels per line. The VGA color model is
unusual. The ATTR contains a 16-entry color palette with
6 bits per entry. Except for 8 BPP modes, all VGA configu-
rations drive four bits of pixel data into the palette, which
produces a 6-bit result. Based on various control regis-
ters, this value is then combined with other register con-
tents to produce an 8-bit index into the DAC. There is a
ColorPlaneEnable register to mask bits out of the pixel
data before it goes to the palette; this is used to emulate
four-color CGA modes by ignoring the top two bits of each
pixel. In 8 BPP modes, the palette is bypassed and the
pixel data goes directly to the DAC
5.2.3 GXm VGA Hardware
The GXm processor core contains hardware to detect
VGA accesses and generate SMI interrupts. The graphics
pipeline contains hardware to detect and process reads
and writes to VGA memory. The VGA memory on the
GXm processor is partitioned from system memory. The
GXm processor has the following hardware components
to assist the VGA emulation software.
• SMI Generation
• VGA Range Detection
• VGA Sequencer
• VGA Write/Read Path
• VGA Address Generator
• VGA Memory
5.2.3.1 SMI Generation
VGA emulation software is notified of VGA memory
accesses by an SMI generated in dedicated circuitry in
the processor core that detects and traps memory
accesses. The SMI generation hardware for VGA memory
addresses is in the second stage of instruction decoding
on the processor core. This is the earliest stage of instruc-
tion decode where virtual addresses have been translated
to physical addresses. Trapping after the execution stage
is impractical, because memory write buffering will allow
subsequent instructions to execute.
The VGA emulation code requires the SMI to be gener-
ated immediately when a VGA access occurs. The SMI
generation hardware can optionally exclude areas of VGA
memory, based on a 32-bit register which has a control bit
for each 2 KB region of the VGA memory window. The
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