GXM Datasheet, PDF (56/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Processor Programming (Continued)
Cache Test Registers
The processor’s 16 KB on-chip cache is a four-way set
associative memory that is configured as write-back
cache. Each cache set contains 256 entries. Each entry
consists of a 20-bit tag address, a 16-byte data field, a
valid bit, and four dirty bits.
The 20-bit tag represents the high-order 20 bits of the
physical address. The 16-byte data represents the 16
bytes of data currently in memory at the physical address
represented by the tag. The valid bit indicates whether the
data bytes in the cache actually contain valid data. The
four dirty bits indicate if the data bytes in the cache have
been modified internally without updating external mem-
ory (write-back configuration). Each dirty bit indicates the
status for one double-word (4 bytes) within the 16-byte
data field.
For each line in the cache, there are three LRU bits that
indicate which of the four sets was most recently
accessed. A line is selected using bits [11:4] of the physi-
cal address. Figure 3-1 illustrates the CPU cache archi-
tecture.
The CPU contains three test registers (TR5-TR3) that
allow testing of its internal cache. Bit definitions for the
cache test registers are shown in Table 3-17. Using a 16-
byte cache fill buffer and a 16-byte cache flush buffer,
cache reads and writes may be performed.
.
D
E
A11-A4 ^C
O
D
E
Line
Address
255
254
.
.
0
= Cache Entry (153 bits)
Tag Address (20 bits)
Data (128 bits)
Valid Status (1 bit)
Dirty Status (4 bits)
Set 0
.
.
152 --- 0
Set 1
Set 2
Set 3
LRU
.
.
152 --- 0
.
.
152 --- 0
.
.
152 --- 0
.
.
2 --- 0
Figure 3-1. CPU Cache Architecture
Table 3-16. Cache Test Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR5 Register (R/W)
TR4 Register (R/W)
RSVD
Cache Tag Address
Line Selection
Set/ Control
DWORD Bits
0
LRU Bits
Dirty Bits
0 00
TR3 Register (R/W)
Cache Data
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