GXM Datasheet, PDF (151/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Integrated Functions (Continued)
4.5.14 Palette Access Registers
These registers are used for accessing the internal palette
RAM and extensions. In addition to the standard 256
entries for 8 BPP color translation, the GXm processor
palette has extensions for cursor colors and overscan
(border) color.
The Palette Access Register group consists of four 32-bit
registers located at GX_BASE+8370h-837Ch. These reg-
isters are described below and Table 4-35 gives their bit
formats.
• Display Controller Palette Address
(DC_PAL_ADDRESS)
- This register should be written with the address
(index) location to be used for the next access to the
DC_PAL_DATA register.
• Display Controller Palette Data (DC_PAL_DATA)
- Contains the data for a palette access cycle.
• Display Controller Display FIFO Diagnostic
(DC_DFIFO_DIAG)
- This register is provided to enable testability of the
Display FIFO RAM.
• Display Controller Compression FIFO Diagnostic
(DC_CFIFO_DIAG)
- This register is provided to enable testability of the
Compressed Line Buffer (FIFO) RAM.
Table 4-35. Display Controller Palette and RAM Diagnostic Registers
Bit
Name
Description
GX_BASE+8370h-8373h
DC_PAL_ADDRESS Register (R/W)
Default Value = xxxxxxxxh
31:9
RSVD
Reserved: Set to 0.
8:0
PALETTE_ADDR Palette Address: This 9-bit field specifies the address to be used for the next access to the
DC_PAL_DATA register. Each access to the data register will automatically increment the palette
address register. If non-sequential access is made to the palette, the address register must be
loaded between each non-sequential data block. The address ranges are as follows.
Address
0h - FFh
100h
101h
102h
103h
104h
105h - 1FFh
Color
Standard Palette Colors
Cursor Color 0
Cursor Color 1
Reserved
Reserved
Overscan Color
Not Valid
Note that in general, 18-bit values will be loaded for all color extensions. However, if a 16 BPP mode
is active, only the appropriate most significant bits will be used (5-5-5 or 5-6-5). If an 8 BPP display
mode is active and an external RAMDAC is used, the cursor index will be obtained from the
DC_CURSOR_COLOR register. The border index will be obtained from the DC_BORDER_COLOR
register.
GX_BASE+8374h-8377h
DC_PAL_DATA Register (R/W)
Default Value = xxxxxxxxh
31:18
RSVD
Reserved: Set to 0.
17:0
PALETTE_DATA Palette Data: This 18-bit field contains the read or write data for a palette access.
Note: When a read or write to the palette RAM occurs, the previous output value will be held for one additional DOTCLK period. This
effect should go unnoticed and will provide for sparkle-free update. Prior to a read or write to this register, the
DC_PAL_ADDRESS register should be loaded with the appropriate address. The address automatically increments after each
access to this register, so for sequential access, the address register need only be loaded once
GX_BASE+8378h-837Bh
DC_DFIFO_DIAG Register (R/W)
Default Value = xxxxxxxxh
Revision 3.1
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