GXM Datasheet, PDF (187/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Electrical Specifications (Continued)
Table 7-7. Clock Signals
180 MHz (6x)
(Note)
200 MHz (6x)
(Note)
233 MHz (7x)
(Note)
266 MHz (8x)
(Note)
Symbol ParameterT
Min
Max
Min
Max
Min
Max
Min
t1
SYSCLK Period
33.3
30.0
30.0
t2
SYSCLK Period Stability
±250
±250
±250
t3
SYSCLK High Time
10
10
10
10
t4
SYSCLK Low Time
10
10
10
10
t5
SYSCLK Fall Time
0.15
2.0
0.15
2.0
0.15
2.0
0.15
t6
SYSCLK Rise Time
0.15
2.0
0.15
2.0
0.15
2.0
0.15
t7
DCLK Period
7.3
7.3
7.3
7.3
t8
DCLK Rise/Fall Time
3.0
3.0
3.0
t9
SDCLK_OUT,
14.5
19.5
13
17
11
16
10
SDCLK[3:0] Period
t10
SDCLK_OUT,
7.5
6.5
5.5
5
SDCLK[3:0] High Time
t11
SDCLK_OUT,
7.5
6.5
5.5
5
SDCLK[3:0] Low Time
t12
SDCLK_OUT,
0.15
2.0
0.15
2.0
0.15
2.0
0.15
SDCLK[3:0] Fall Time
t13
SDCLK_OUT,
0.15
2.0
0.15
2.0
0.15
2.0
0.15
SDCLK[3:0] Rise Time
Note: SDCLK timings (t9-t13) assume an SDCLK that is a "divide by 3" from the internal core clock. Hence:
180 MHz (6x) = 60.0 MHz SDCLK
200 MHz (6x) = 66.7 MHz SDCLK
233 MHz (7x) = 77.7 MHz SDCLK
266 MHz (8x) = 88.7 MHz SDCLK
Max
30.0
±250
2.0
2.0
3.0
13
2.0
2.0
Units
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t3
V_{IH (Min)}
1.5V
V_{IL (Max)}
SYSCLK
t6
t4
t5
Figure 7-1 SYSCLK Timing and Measurement Points
Revision 3.1
187
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