GXM Datasheet, PDF (64/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Processor Programming (Continued)
Logical Address
Segment Selector
15
INDEX
0
INSTRUCTION OFFSET
Logical
Address
x 16
+
p
Base
Linear
Physical
Address
Address
Address
p= Paging Mechanism for Virtual 8086 Mode only
Real and Virtual 8086 Modes
Segment
Main Memory
Logical Address
Segment Selector
15
3 21 0
INDEX
TI RPL INSTRUCTION OFFSET
x8
Segment Descriptor
+
p
Base
Linear
Physical
Address
Address
Address
GDT or LDT Descriptor Table
p = Paging Mechanism
Segment
Main Memory
Protective Mode
Figure 3-6. Selector Mechanisms
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