GXM Datasheet, PDF (24/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Signal Definitions (Continued)
2.2 SIGNAL DESCRIPTIONS
2.2.1 System Interface Signals
Signal Name
BGA SPGA
Pin No. Pin No.
SYSCLK
P26
V34
CLKMODE[2:0]
M1, L1, G3, R2,
M3
S1
RESET
J3
M2
Type
I
I
I
Description
System Clock
System Clock runs synchronously with the PCI bus. The internal
clock of the GXm processor is generated by an internal PLL
which multiplies the SYSCLK input and can run up to eight times
faster. The SYSCLK to core clock multiplier is configured using
the CLKMOD[2:0] inputs.
The SYSCLK input is a fixed frequency which can only be
stopped or varied when the GXm processor is in a full 3V Sus-
pend. (Section 6.4 “3-Volt Suspend Mode” on page 174 for
details regarding this mode.)
Clock Mode
These signals are used to set the core clock multiplier. The PCI
clock "SYSCLK" is multiplied by the value programmed by CLK-
MODE[2:0] to generate the GXm processor’s core clock.
CLKMODE2 is valid only for GXm processor revision 4.0 and up.
The value read from DIR1 (Device ID Register 1, refer to
page 51) affects the definition of the CLKMODE pins.
If DIR1 = 30h-33h then CLKMODE[1:0]:
00 = SYSCLK multiplied by 4 (Test mode only)
01 = SYSCLK multiplied by 6
10 = SYSCLK multiplied by 7
11 = SYSCLK multiplied by 5
If DIR1 = 34h-4Fh then CLKMODE[1:0]:
00 = SYSCLK multiplied by 4 (Test mode only)
01 = SYSCLK multiplied by 6
10 = SYSCLK multiplied by 7
11 = SYSCLK multiplied by 8
If DIR1 > or = 50h then CLKMODE[2:0]:
000 = SYSCLK multiplied by 4 (Test mode only)
001 = SYSCLK multiplied by 10
010 = SYSCLK multiplied by 9
011 = SYSCLK multiplied by 5
100 = SYSCLK multiplied by 4
101 = SYSCLK multiplied by 6
110 = SYSCLK multiplied by 7
111 = SYSCLK multiplied by 8
Reset
RESET aborts all operations in progress and places the
GXm processor into a reset state. RESET forces the CPU and
peripheral functions to begin executing at a known state. All data
in the on-chip cache is invalidated.
RESET is an asynchronous input but must meet specified setup
and hold times to guarantee recognition at a particular clock
edge. This input is typically generated during the Power-On-
Reset sequence.
Note: Warm Reset does not require an input on the GXm pro-
cessor since the function is virtualized using SMM.
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