GXM Datasheet, PDF (10/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Architecture Overview (Continued)
1.5.2 Display Controller
The display port is a direct interface to the CS5530 which
drives a TFT flat panel display, LCD panel, or a CRT dis-
play.
The display controller (video generator) retrieves image
data from the frame buffer region of memory, performs a
color-look-up if required, inserts the cursor overlay into
the pixel stream, generates display timing, and formats
the pixel data for output to a variety of display devices.
The display controller contains Display Compression
Technology (DCT) that allows the GXm processor to
refresh the display from a compressed copy of the frame
buffer. DCT typically decreases the screen-refresh band-
width requirement by a factor of 15 to 20, further minimiz-
ing bandwidth contention.
1.5.3 XpressRAM Memory Subsystem
The memory controller drives a 64-bit SDRAM port
directly. The SDRAM memory array contains both the
main system memory and the graphics frame buffer. Up to
four module banks of SDRAM are supported. Each mod-
ule bank will have two or four component banks depend-
ing on the memory size and organization. The maximum
configuration is four module banks with four component
banks providing a total of 16 open banks. The maximum
memory size is 1 GB.
The memory controller handles multiple requests for
memory data from the GXm processor, the graphics
accelerator and the display controller. The memory con-
troller contains extensive buffering logic that helps mini-
mize contention for memory bandwidth between graphics
and CPU requests. The memory controller cooperates
with the internal bus controller to determine the cacheabil-
ity of all memory references.
1.5.4 PCI Controller
The GXm processor incorporates a full-function PCI inter-
face module that includes the PCI arbiter. All accesses to
external I/O devices are sent over the PCI bus, although
most memory accesses are serviced by the SDRAM con-
troller. The Internal Bus Interface Unit contains address
mapping logic that determines if memory accesses are
targeted for the SDRAM or for the PCI bus.
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