GXM Datasheet, PDF (229/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Instruction Set (Continued)
9.5 MMX INSTRUCTION SET
The CPU is functionally divided into the FPU unit, and the
integer unit. The FPU has been extended to process both
MMX instructions and floating point instructions in parallel
with the integer unit. Revision 3.1
For example, when the integer unit detects a MMX
instruction, the instruction passes to the FPU unit for exe-
cution. The integer unit continues to execute instructions
while the FPU unit executes the MMX instruction. If
another MMX instruction is encountered, the second
MMX instruction is placed in the MMX queue. Up to four
MMX instructions can be queued.
The MMX instruction set is summarized in Table 9-31 on
page 230. The abbreviations used in the table are listed in
Table 9-30.
Table 9-30. MMX Instruction Set Table Legend
Abbreviation
Description
<----
[11 mm reg]
mm
reg
<--sat--
<--move--
[byte]
[word]
[dword]
[qword]
[sign xxx]
mm1, mm2
mod r/m
pack
packdw
packwb
Result written
Binary or binary groups of digits
One of eight 64-bit MMX registers
A general purpose register
If required, the resultant data is saturated
to remain in the associated data range
Source data is moved to result location
Eight 8-bit bytes are processed in parallel
Four 16-bit word are processed in parallel
Two 32-bit double words are processed in
parallel
One 64-bit quad word is processed
The byte, word, double word or quad word
most significant bit is a sign bit
MMX Register 1, MMX Register 2
Mod and r/m byte encoding (page 6-6 of
this manual)
Source data is truncated or saturated to
next smaller data size, then concatenated.
Pack two double words from source and
two double words from destination into four
words in destination register.
Pack four words from source and four
words from destination into eight bytes in
destination register.
Revision 3.1
229
www.national.com