GXM Datasheet, PDF (75/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Processor Programming (Continued)
Single-step operation is enabled by setting the TF bit (bit
8) in the EFLAGS register. When TF is set, the CPU gen-
erates a debug exception (vector 1) after the execution of
every instruction. Data breakpoints also generate a debug
exception and are specified by loading the debug regis-
ters (DR0-DR7) with the appropriate values.
A Fault exception is reported before completion of the
instruction that generated the exception. By reporting the
fault before instruction completion, the processor is left in
a state that allows the instruction to be restarted and the
effects of the faulting instruction to be nullified. Fault
exceptions include divide-by-zero errors, invalid opcodes,
page faults and coprocessor errors. Debug exceptions
(vector 1) are also handled as faults (except for data
breakpoints and single-step operations). After execution
of the fault service routine, the instruction pointer points to
the instruction that caused the fault.
An Abort exception is a type of fault exception that is
severe enough that the CPU cannot restart the program at
the faulting instruction. The double fault (vector 8) is the
only abort exception that occurs on the processor.
3.10.3 Interrupt Vectors
When the processor services an interrupt or exception,
the current program’s instruction pointer and flags are
pushed onto the stack to allow resumption of execution of
the interrupted program. In protected mode, the processor
also saves an error code for some exceptions. Program
control is then transferred to the interrupt handler (also
called the interrupt service routine). Upon execution of an
IRET at the end of the service routine, program execution
resumes at the instruction pointer address saved on the
stack when the interrupt was serviced.
3.10.3.1 Interrupt Vector Assignments
Each interrupt (except SMI#) and exception is assigned
one of 256 interrupt vector numbers as shown in Table 3-
29. The first 32 interrupt vector assignments are defined
or reserved. INT instructions acting as software interrupts
may use any of interrupt vectors, 0 through 255.
The non-maskable hardware interrupt (NMI) is assigned
vector 2. Illegal opcodes including faulty FPU instructions
will cause an illegal opcode exception, interrupt vector 6.
NMI interrupts are enabled by setting bit 2 of the CCR7
register (Index EBh[2] = 1, see Table 3-11 on page 49 for
register format).
In response to a maskable hardware interrupt (INTR), the
processor issues interrupt acknowledge bus cycles used to
read the vector number from external hardware. These vec-
tors should be in the range 32 to 255 as vectors 0 to 31 are
predefined. In PCs, vectors 8 through 15 are used.
3.10.3.2 Interrupt Descriptor Table
The interrupt vector number is used by the processor to
locate an entry in the interrupt descriptor table (IDT). In
real mode, each IDT entry consists of a four-byte far
pointer to the beginning of the corresponding interrupt
service routine. In protected mode, each IDT entry is an
8-byte descriptor. The Interrupt Descriptor Table Register
(IDTR) specifies the beginning address and limit of the
IDT. Following reset, the IDTR contains a base address of
0h with a limit of 3FFh.
The IDT can be located anywhere in physical memory as
determined by the IDTR. The IDT may contain different
types of descriptors: interrupt gates, trap gates and task
gates. Interrupt gates are used primarily to enter a hard-
ware interrupt handler. Trap gates are generally used to
enter an exception handler or software interrupt handler. If
an interrupt gate is used, the Interrupt Enable Flag (IF) in
the EFLAGS register is cleared before the interrupt han-
dler is entered. Task gates are used to make the transition
to a new task.
Table 3-29. Interrupt Vector Assignments
Interrupt
Vector
Function
Exception
Type
0
Divide error
Fault
1
Debug exception
Trap/Fault*
2
NMI interrupt
3
Breakpoint
Trap
4
Interrupt on overflow
Trap
5
BOUND range exceeded
Fault
6
Invalid opcode
Fault
7
Device not available
Fault
8
Double fault
Abort
9
Reserved
10
Invalid TSS
Fault
11
Segment not present
Fault
12
Stack fault
Fault
13
General protection fault
Trap/Fault
14
Page fault
Fault
15
Reserved
16
FPU error
Fault
17
Alignment check exception
Fault
18:31
Reserved
32:55
Maskable hardware interrupts
Trap
0:255
Programmed interrupt
Trap
Note: *Data breakpoints and single steps are traps. All other
debug exceptions are faults.
Revision 3.1
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