GXM Datasheet, PDF (167/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Virtual Subsystem Architecture (Continued)
CPU to VGA memory are broken down into multiple byte
accesses by the sequencer. For example, a word write to
A0000h (in a VGA graphics mode) is processed as if it
were two-byte write operations to A0000h and A0001h.
5.1.1.3 Address Mapping
When a VGA card sees an address on the host bus, bits
[31:15] determine whether the transaction is for the VGA.
Depending on the mode, addresses 000AXXXX,
000B{0XXX}XXX, or 000B{1XXX}XXXX can decode into
VGA space. If the access is for the VGA, bits [15:0] pro-
vide the DWORD address into the frame buffer (however,
see odd/even and Chain 4 modes, below). Thus, each
byte address on the host bus addresses a DWORD in
VGA memory.
On a write transaction, the byte enables are normally
driven from the sequencer’s MapMask register. The VGA
has two other write address mappings that modify this
behavior. In odd/even (Chain 2) write mode, bit 0 of the
address is used to enable bytes 0 and 2 (if zero) or bytes
1 and 3 (if one). In addition, the address presented to the
frame buffer has bit 0 replaced with the PageBit field of
the Miscellaneous Output register. Chain 4 write mode is
similar; only one of the four byte enables is asserted,
based on bits [1:0] of the address, and bits [1:0] of the
frame buffer address are set to zero. In each of these
modes, the MapMask enables are logically ANDed into
the enables that result from the address.
5.2 GXM VIRTUAL VGA
The GXm processor provides VGA compatibility through a
mixture of hardware and software. The processor core
contains SMI generation hardware for VGA memory write
operations. The bus controller contains SMI generation
hardware for VGA I/O read and write operations. The
graphics pipeline contains hardware to detect and pro-
cess reads and writes to VGA memory. VGA memory is
partitioned from system memory.
5.2.1 Datapath Elements
The graphics controller contains several elements that
convert between host data and frame buffer data.
The rotator simply rotates the byte written from the host
by 0 to 7 bits to the right, based on the RotateCount field
of the DataRotate register. It has no effect in the read
path.
The display latch is a 32-bit register that is loaded on
every read access to the frame buffer. All 32 bits of the
frame buffer DWORDs are loaded into the latch.
The write-mode unit converts a byte from the host into a
32-bit value. A VGA has four write modes:
• Write Mode 0:
- Bit n of byte b comes from one of two places,
depending on bit b of the EnableSetReset register. If
that bit is zero, it comes from bit n of the host data. If
that bit is one, it comes from bit b of the SetReset
register. This mode allows the programmer to set
some planes from the host data and the others from
SetReset.
• Write Mode 1:
- All 32 bits come directly out of the display latch; the
host data is ignored. This mode is used for screen-
to-screen copies.
• Write Mode 2:
- Bit n of byte b comes from bit b of the host data; that
is, the four LSBs of the host data are each replicated
through a byte of the result. In conjunction with the
BitMask register, this mode allows the programmer
to directly write a 4-bit color to one or more pixels.
• Write Mode 3:
- Bit n of byte b comes from bit b of the SetReset
register. The host data is ANDed with the BitMask
register to provide the bit mask for the write (see
below).
The read mode unit converts a 32-bit value from the
frame buffer into a byte. A VGA has two read modes:
• Read Mode 0:
- One of the four bytes from the frame buffer is
returned, based on the value of the ReadMapSelect
register. In Chain 4 mode, bits [1:0] of the read
address select a plane. In odd/even read mode, bit 0
of the read address replaces bit 0 of ReadMapSe-
lect.
• Read Mode 1:
- Bit n of the result is set to 1 if bit n in every byte b
matches bit b of the ColorCompare register; other-
wise it is set to 0. There is a ColorDon’tCare register
that can exclude planes from this comparison. In
four-plane graphics modes, this provides a conver-
sion from 4 BPP to 1 BPP.
The ALU is a simple two-operand ROP unit that operates
on writes. Its operating modes are COPY, AND, OR, and
XOR. The 32-bit inputs are:
1) the output of the write-mode unit and
2) the display latch (not necessarily the value at the
frame buffer address of the write).
An application that wishes to performs ROPs on the
source and destination must first byte read the address (to
load the latch) and then immediately write a byte to the
same address. The ALU has no effect in Write Mode 1.
The bit mask unit does not provide a true bit mask.
Instead, it selects between the ALU output and the display
latch. The mask is an 8-bit value, and bit n of the mask
makes the selection for bit n of all four bytes of the result
(a zero selects the latch). No bit masking occurs in Write
Mode 1.
The VGA hardware of the GXm processor does not imple-
ment Write Mode 1 directly, but it can be indirectly imple-
mented by setting the BitMask to zero and the ALU mode
to COPY.
Revision 3.1
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