GXM Datasheet, PDF (45/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Processor Programming (Continued)
3.3.2.1 Control Registers
A map of the Control Registers (CR0, CR2, CR3, and
CR4) is shown in Table 3-6 and the bit definitions are given
in Table 3-7. (These registers should not be confused with
the CRRn registers.) The CR0 register contains system
control bits which configure operating modes and indicate
the general state of the CPU. The lower 16 bits of CR0 are
referred to as the Machine Status Word (MSW).
When operating in real mode, any program can read and
write the control registers. In protected mode, however,
only privilege level 0 (most-privileged) programs can read
and write these registers.
Table 3-6. Control Registers Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR4 Register
CR3 Register
CR2 Register
CR1 Register
CR0 Register
PCN
G DW
Control Register 4 (R/W)
RSVD
T RSVD
S
C
Control Register 3 (R/W)
PDBR (Page Directory Base Register)
RSVD
0 0 RSVD
Control Register 2 (R/W)
PFLA (Page Fault Linear Address)
Control Register 1 (R/W)
RSVD
Control Register 0 (R/W)
RSVD
A RW
MS P
V
D
RSVD
NRT EMP
E S SMP E
V
D
Machine Status Word (MSW)
Table 3-7. CR4-CR0 Bit Definitions
Bit Name Description
CR4 Register
31:3
2
RSVD
TSC
1:0 RSVD
CR3 Register
31:12
11:0
PDBR
RSVD
CR2 Register
31:0 PFLA
CR1 Register
31:0 RSVD
CR0 Register
31
PG
Control Register 4 (R/W)
Reserved: Set to 0 (always returns 0 when read).
Time Stamp Counter Instruction:
If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.
If = 0 RDTSC instruction enabled for all CPL states.
Reserved: Set to 0 (always returns 0 when read).
Control Register 3 (R/W)
Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.
Reserved: Set to 0.
Control Register 2 (R/W)
Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the
address that caused the page fault.
Control Register 1 (R/W)
Reserved
Control Register 0 (R/W)
Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the
state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change
take effect.
Revision 3.1
45
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